SP3486 Datasheet, PDF (3/9 Pages) Sipex Corporation – +3.3V Low Power Quad RS-485/RS-422 Line Drivers

PINOUT — SP3486
DI₁ 1
1
DO₁A 2
DO₁B 3
EN 4
DO₂B 5
DO₂A 6
2
DI₂ 7
GND 8
SP3486 ^{16 V}CC
15 DI₄
4
14 DO₄A
13 DO₄B
12 EN
11 DO₃B
10 DO₃A
3
9 DI₃
SP3486 PINOUT
Pin 1 — DI₁ — Driver 1 Input — If Driver 1 output
is enabled, logic 0 on DI₁ forces driver output
DO₁A low and DO₁B high. A logic 1 on DI₁ with
Driver 1 output enabled forces driver DO₁A high
and DO₁B low.
Pin 2 — DO₁A — Driver 1 output A.
Pin 3 — DO₁B — Driver 1 output B.
Pin 4 — EN — Driver Output Enable. Please refer
to SP3486 Truth Table (1).
Pin 5 — DO₂B — Driver 2 output B.
Pin 6 — DO₂A — Driver 2 output A.
Pin 7 — DI₂ — Driver 2 Input — If Driver 2 output
is enabled, logic 0 on DI₂ forces driver output
DO₂A low and DO₂B high. A logic 1 on DI₂ with
Driver 2 output enabled forces driver DO₂A high
and DO₂B low.
D
VCC
R
VOD
R
VOC
GENERATOR
(NOTE 1)
VDM
S1
D
50Ω
VCC
RL = 27Ω
OUT
CL = 15PF
(NOTE 2)
VOM =
VOH + VOL
2
1.5V
Figure 2. Driver Propagation Delay Test Circuit
Pin 8 — GND — Digital Ground.
Pin 9 — DI — Driver 3 Input — If Driver 3 output
3
is enabled, logic 0 on DI forces driver output
3
DO A low and DO B high. A logic 1 on DI with
3
3
3
Driver 3 output enabled forces driver DO₃A high
and DO B low.
3
Pin 10 — DO₃A — Driver 3 output A.
Pin 11 — DO₃B — Driver 3 output B.
Pin 12 — EN — Driver Output Disable. Please
refer to SP486 Truth Table (1).
GENERATOR
(NOTE 1)
S1
D
CL = 50pF
(NOTE 2)
50Ω
OUT
RL = 110Ω
VOM =
VOH + VOL
2
1.5V
Figure 3. Driver Enable and Disable Timing Circuit,
Output HIGH
S1
0V OR 3V
D
VCC
RL = 110Ω
OUT
GENERATOR
(NOTE 1)
CL = 50pF
(NOTE 2)
50Ω
Figure 1. Driver DC Test Load Circuit
Figure 4. Driver Enable and Disable Timing Circuit,
Output LOW
10/15/02
SP3486/3487 Low Power Quad RS485/422 Line Drivers
3
© Copyright 2002 Sipex Corporation