SP3508 Datasheet, PDF (24/33 Pages) Sipex Corporation – Rugged 3.3V, 20Mbps, 8 Channel Multiprotocol Transceiver with Programmable DCE/DTE and Termination Resistors

The same receivers also incorporate a termination
network internally for V.35 applications. For
V.35, the receiver input termination is a “Y”
termination consisting of two 51Ω resistors
connected in series and a 124Ω resistor connected
between the two 50Ω resistors and GND. The
receiver itself is identical to the V.11 receiver.
The differential receivers can be configured to
be ITU-T-V.10 single-ended receivers by
internally connecting the non-inverting input to
ground. This is internally done by default from
the decoder. The non-inverting input is rerouted
to V10GND and can be grounded separately.
The ITU-T-V.10 receivers can operate over
120Kbps and are used in RS-449/V.36, E1A-
530, E1A-530A and X.21 modes as Category II
signals as indicated by their corresponding
specifications. All receivers include an enable/
disable line for disabling the receiver output
allowing convenient half-duplex configurations.
The enable pins will either enable or disable the
output of the receivers according to the
appropriate active logic illustrated on Figure 44.
The receiver’s enable lines include an internal
pull-up or pull-down device, depending on the
active polarity of the receiver, that enables the
receiver upon power up if the enable lines are left
floating. During disabled conditions, the receiver
outputs will be at a high impedance state. If the
receiver is disabled any associated termination is
also disconnected from the inputs.
FEATURES
All receivers include a fail-safe feature that
outputs a logic high when the receiver inputs are
open, terminated but open, or shorted together.
For single-ended V.28 and V.10 receivers, there
are internal 5kΩ pull-down resistors on the inputs
which produces a logic high (“1”) at the receiver
outputs. The differential receivers have a
proprietary circuit that detect open or shorted
inputs and if so, will produce a logic HIGH (“1”)
at the receiver output.
CHARGE PUMP
SP3508 uses an internal capacitive charge pump
to generate Vdd and Vss. The design is Sipex
patented (5,306,954) four-phased voltage shift-
ing charge pump converters that converts the
input voltage of 3.3V to nominal output volt-
ages of +/-6V (Vdd & Vss1). SP3508 also in-
cludes an inverter block that inverts Vcc to -Vcc
(Vss2). There is a free-running oscillator that
controls the four phases of the voltage shifting.
A description of each phase follows.
4-phased doubler pump
Phase 1
-V_SS1 charge storage -During this phase of the
clock cycle, the positive side of capacitors C1
and C2 are initially charged to V_CC. C1+ is then
switched to ground and the charge in C1- is
transferred to C2-. Since C2+ is connected to
V_CC, the voltage potential across capacitor C2 is
now 2xV_CC.
V_CC = +3V
+
C_{1 –}
–3V
+3V
+
C_{2 –}
–3V
C_VDD
+ – _{VDD Storage Capacitor}
– + _{VSS1 Storage Capacitor}
C_VSS1
Figure 45. Charge Pump - Phase 1.
Date: 06/14/04
SP3508 Enhanced WAN Multi–Mode Serial Transceiver
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© Copyright 2004 Sipex Corporation