SP508EB Datasheet, PDF (2/10 Pages) Sipex Corporation – Evaluation Board Manual

V_CC
10µF
* Pins 1,26,45,64,71,77,80,84,88,93,98 = VCC
** Pins 2,25,44,52,68,74,82,86,91,96 = GND
Pins 24 and 76 are no connects.
Circuit #
103
113
113
105
108
109
140
141
Driver applies for DCE only on pins 5 and 12.
Receiver applies for DTE only on Pins 5 and 12.
Driver applies for DCE only on Pins 8 and 10.
Receiver applies for DTE only on Pins 8 and 10.
105
115
114
106
107
109
125
142
GND
MODE
SHUTDOWN
V.35
EIA-530
RS-232
EIA-530A
RS-449
X.21
DECODER
D0 D1 D2
1 11
0 01
0 10
0 11
1 00
1 01
1 10
V_CC
GND
Figure 1
rev. 7/7/03
1µF
1µF
1µF
73 72
V_DD C1+
V_CC*
69 70 67
C1- C2+ C2-
V_SS 66
GND * *
TxD 28
TxCE 29
ST 30
RTS 31
DTR 32
DCDDCE 33
97 SD(a)
100 SD(b)
92 TT(a)
95 TT(b)
87 ST(a)
90 ST(b)
83 RS(a)
85 RS(b)
75 TR(a)
78 TR(b)
81 RRC(a)
79 RRC(b)
RL 34
65 RL(a)
LL 35
63 LL(a)
1µF
25-Pin D-Sub
Connector Pins
2
14
24
11
4
19
20
23
21
18
ON Loopback
OFF No Loopback
RxD 36
RxC 37
TxC 38
CTS 39
DSR 40
DCDDTE 41
RI 42
TM 43
3 SDEN
4 TTEN
5 STEN
6 RSEN
7 TREN
8 RRSEN
9 RLEN
10 LLEN
11 RDEN
12 RTEN
13 TxCEN
14 CSEN
15 DMEN
16 RRTEN
17 ICEN
18 TMEN
48 SD(a)
47 SD(b)
50 TT(a)
49 TT(b)
53 ST(a)
51 ST(b)
55 RS(a)
54 RS(b)
57 TR(a)
56 TR(b)
60 RRC(a)
59 RRC(b)
61 RL(a)
62 LL(a)
D0
19
D1
20
D2
21
LOOPBACK 27
LATCH 23
TERM_OFF 22
1
0
0
1
V_CC
3
16
17
9
15&
12&
5
13
6
22
8&
10&
22
25
1
Logic high
0
Logic low
V35TGND1 99
V35TGND1 94
V35TGND1 89
V35TGND1 46
V35TGND1 58
1
2
1
2
1
2
1
2
1
2
GND
Connect jumper to enable internal cable termination
SP508 Evaluation Board Manual
2
© Copyright 2003 Sipex Corporation