SP6650 Datasheet, PDF (15/17 Pages) Sipex Corporation – High Efficiency 600mA Synchronous Buck Regulator Ideal for portable designs powered with Li Ion battery

Layout Considerations
Proper layout is a very important part of the on-
board power supply, affecting normal function-
ality of the DC-DC converter itself and EMI.
Because of the high frequency switching of the
converter, the traces that couple an electric field
can conduct currents under the AC voltages
across the parasitic capacitance. Magnetic field
coupling traces can induce currents like trans-
formers.
To avoid an excessive interference between the
converter and the other active components on the
board, some rules should be followed.
Avoid injecting noise into the sensitive part of
the circuit via the GND Plane. Input and output
capacitors conduct the current through the GND
Plane and high frequency components of the
current can degrade the sensitive circuitry. Sepa-
rate the power and signal grounds and connect
them at one point to minimize the noise injected
from the power ground to the signal ground.
"Star" connection of the ground traces is shown
on Figure 26, where GND is the minus pole of the
output capacitor.
Power loops on the input and output of the
converter should be laid out with the shortest and
widest traces possible. The longer and narrower
the trace, the higher the resistance and induc-
tance it will have. The AC current in long traces
radiates EMI noise affecting the sensitive cir-
cuits. The length of traces in series with the
capacitors increases its ESR and ESL and reduc-
ing their effectiveness at high frequencies. There-
fore put the input capacitor as close to the appropri-
ate pins of the converter as possible and output
capacitor close to the inductor.
The external voltage feed back network should
be placed very close to the FB pin as well as
bypass capacitor C4. Any noise traces like the Lx
pin should be kept away from the voltage feed
back network and separated from it by using
power ground copper to minimize EMI.
3
100k
R1
10Ω
1
C1
1µF
2.7 - 6.5V DC
SP6650
1
PVIN
LX ¹⁰
2 _VIN
PGND ⁹
3 _BLON
GND ⁸
4
5
+
C2
47µF
ILIM
SDN
7
VOUT
FB ⁶
L1
22µH
C4
470pF
GND_ SIGNAL
R2
100kΩ
2.5V
+
R3
100kΩ
C3
47µF
Figure 21. Application circuit with highlighted power traces.
Date: 5/25/04
SP6650 High Efficiency 600mA Synchronous Buck Regulator
15
© Copyright 2004 Sipex Corporation