SP505AN Datasheet, PDF (15/30 Pages) Sipex Corporation – Multi-Protocol Serial Transceivers

Figure 27. SP507 TxCE at 12MHz over 86ft.
The V.35 interface was selected because the V.35
signal has low voltage differential amplitude, which
is more susceptible to noise compared to other higher
amplitude signals such as V.11 or RS-485. The small
amplitude of 0.55V can easily be affected by noise
caused by various environmental effects.
SP506 and SP507 driver performance was
characterized over 6ft., 26ft., 56ft., 86ft, 106ft., 126ft.,
and 156ft. V.35 cable lengths. The frequency
measured are from 1.544MHz, 2.048MHz,
3.152MHz, 6.312MHz, 8.192MHz, 9.600MHz,
10MHz, and 12MHz. The scope photos and graphs
on Figures 9 through 27 illustrate the some of these
measurements.
The Fireberd 6000A was able to synchronize with
the incoming TxCE clock signal and read the TxD
output data stream up to a 12MHz clock without any
bit errors. This implies that the clock source had
sufficient amplitude and was stable enough for the
DCE receiver to read back and synchronize the data
on the clock's rising edge. The transmission was
successful up to 12MHz with 86 feet of V.35 cable
without bit errors. Further cable length degraded the
signal to a point where the receiver was unable to
capture the clock, thus not able to synchronize data
and resulting in bit errors.
One important note is that the signal no longer
adheres to the V.35 specification for Transmitter
Differential Output with Termination (per CCITT
V.35 Section II.3.c) of 0.44V minimum after 56 feet
at 10MHz. However, longer cable lengths and even
12MHz signaling was still readable by the DCE. This
is because the V.35 receiver input sensitivity is
200mV maximum. As the signal amplitude decays to
approximately 400mV_P (832mV_P-P), there is still
enough gain on the signal for the receiver to
successfully read the clock. Although the AC
performance across the system is worse as the
receiver input sensitivity is higher.
The V.35 specification does not take into account any
capacitive loading for the Terminated Transmitter
Output measurement. Therefore it would be unfair to
use the V.35 specification as a criteria for pass/fail in
a real application environment. Signal monotonicity
and duty cycle are the important, measurable
elements to determining a clean and error-free
clock transmission.
Note that these oscilloscope photos are a typical
representation of the SP507's performance in
presence of cabling using our in-house evaluation
board. The system designer should test and
characterize the system in order determine the cable
distance versus speed allowance in the application.
SP505/6/7APN/03
SP505, SP506, SP507 Application Note
15
© Copyright 2000 Sipex Corporation