SP6123 Datasheet, PDF (14/18 Pages) Sipex Corporation – Low Voltage, Synchronous Step-Down PWM Controller Ideal for 2A to 10A, Small Footprint, DC-DC Power Converters

Most electrolytic and tantalum capacitors come
with adequate ESR value to generate a zero below
power supplies’ crossover frequency. This is cru-
cial to a stable close loop system. However, this
same system can become unstable if ceramic out-
put capacitors are used. The low ESR associated
with ceramic capacitors can push the ESR zero
above the crossover frequency and often higher
than 1MHz. In this case, type III compensation is
required to provide additional low frequency zero for
adequate phase margin and thus stable operation.
The design of type III compensation using
SP6123 transconductance error amplifier is quite
straightforward. First, the resonant frequency of
the LC output filter could be derived from
f_r =
1
2π√ L₁C_OUT
= 11.6kHz
The values and references used in all the calcula-
tions agree with the schematic shown in Figure 3.
Select values of R2, C1, R_Z and C_Z to place two
zeros below or equal to the LC resonant fre-
quency. Those two zeros are located at:
f_Z1 =
1
2πR₂C₁
= 6kHz
f_Z2 =
1
2πR_ZC_Z
= 11.7kHz
There is low frequency pole determined by both
the error amplifier gain and feedback gain. It
occurs at
1
f_P1 = _{2π(R2 // R3)CZGMROUT} = 3.25Hz
200
Phase
100
APPLICATIONS INFORMATION
In SP6123, G_M (error amplifier transconductance)
and R_OUT (error amplifier output impedance) are
specified at 0.6ms and 3MΩ, respectively.
For frequencies above the second zero f_Z2, the
feedback gain rises at 20dB/dec and is equal to
A_FB = 2πfR_ZC₁
However, the error amplifier gain A_EA declines
at -20dB/dec due to C_P.
A_EA
=
G_M
2πfC_P
When A_FB is less than A_EA, the compensated
error amplifier gain is dominated by A_FB. As a
result, it shows up as a positive 20dB/dec slope.
However, when the rising A_FB crosses the fall-
ing A_EA at one particular frequency, the com-
pensated error amplifier gain is now solely de-
termined by A_EA. Therefore, the 20dB/dec slope
is converted to a -20dB/dec slope, and the bode
plot demonstrates a double pole at this fre-
quency which is equal to
f_P2
=
1
2π
GM
C_PC₁R_Z
= 221kHz
Select C_P such that f_P2 is located at least a decade
higher than the crossover frequency.
As shown in Figure 4, this type III compensation
generates a close loop system with 50 degree phase
margin and crossover frequency at 20kHz. This
ensures a stable regulated power supply with tight
DC regulation and fast transient response.
0
Gain
-100
-200
10Hz
100Hz
100Hz
1.0kHz
Frequency
10kHz
1.0MHz
10MHz
Figure 4. Bode Plot for schematic shown in Figure 3. V_IN = 3.3V and V_OUT = 1.6V, no load.
Date: 5/25/04
SP6123 Low Voltage, Synchronous Step Down PWM Controller
14
© Copyright 2004 Sipex Corporation