SP504 Datasheet, PDF (14/31 Pages) Sipex Corporation – WAN Multi-Mode Serial Transceiver

V_CC = +5V
+
C_{1 –}
+
C_{2 –}
–10V
C₄
+ – _{VDD Storage Capacitor}
– + _{VSS Storage Capacitor}
C₃
Figure 14a. Charge Pump Phase 2 for ±10V.
V_CC = +5V
+
C_{1 –}
–5V
+5V
+
C_{2 –}
–5V
C₄
+ – _{VDD Storage Capacitor}
– + _{VSS Storage Capacitor}
C₃
Figure 15. Charge Pump Phase 3.
Phase 2 (±10V)
— V_SS transfer — Phase two of the clock con-
nects the negative terminal of C₂ to the V_SS
storage capacitor and the positive terminal of C₂
to ground, and transfers the generated –l0V or
the generated –5V to C₃. Simultaneously, the
positive side of capacitor C ₁ is switched to +5V
and the negative side is connected to ground.
Phase 2 (±5V)
i—nsescwVtei^SdtScth&oeVdVt^Co^DCDgtrocohrueancrdgheaarnsgdteoCrtah_2–^{geieCs—c1}ocnaCnp¹ea⁺cctiiestodrret.ocCoCn^23+-.
The 5V charge from Phase 1 is now transferred
V_CC = +5V
+
C_{1 –}
+
C_{2 –}
–5V
C₄
+ – V_DD Storage Capacitor
– + _{VSS Storage Capacitor}
C₃
Figure 14b. Charge Pump Phase 2 for ±5V.
V_CC = +5V
+
C_{1 –}
+10V
+
C_{2 –}
C₄
+ – V_DD Storage Capacitor
– + _{VSS Storage Capacitor}
C₃
Figure 16. Charge Pump Phase 4.
to the V_SS storage capacitor. V_SS receives a
continuous charge from either C₁ or C₂. With
the C1 capacitor charged to 5V, the cycle begins
again.
Phase 3
— V_DD charge storage — The third phase of the
clock is identical to the first phase — the charge
transferred in C₁ produces –5V in the negative
terminal of C₁, which
side of capacitor C₂.
is applied
Since C₂₊
to
is
the negative
at +5V, the
voltage
output,
Cpo₂₊^{teinsticaolnancercotsesdCt2}o
is l0V.
ground
For the
so that
5V
the
potential on C₂ is only +5V.
+10V
C₂₊
(a)
GND
GND
C_2–
(b)
–10V
+5V
C₂₊
GND
GND
C_2–
–5V
Figure 17. Charge Pump Waveforms
Rev: A Date:1/27/04
SP504 Multi–Mode Serial Transceivers
14
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