SP706P Datasheet, PDF (13/18 Pages) Sipex Corporation – +3.0V/+3.3V Low Power Microprocessor Supervisory Circuits

output is driven HIGH and the µP wants to pull
it LOW, indeterminate logic levels may result.
To correct this, connect a 4.7kΩ resistor
between the RESET output and the µP reset
I/O, as shown if Figure 19. Buffer the
RESET output to other system components.
Negative-Going V_CC Transients
While issuing resets to the µP during power-up,
power-down, and brownout conditions, these
supervisors are relatively immune to short-
duration negative-going V transients (glitches).
CC
It is usually undesirable to reset the µP when V_CC
experiences only small glitches.
Figure 20 shows maximum transient dura-
tion vs. reset-comparator overdrive, for which
reset pulses are not generated. The data was gen-
erated using negative-going V_CC pulses, starting
at 3.3V and ending below the reset threshold by
the magnitude indicated (reset comparator over-
drive). The graph shows the maximum pulse
width a negative-going V_CC transient may
typically have without causing a reset pulse to
be issued. As the amplitude of the transient
increases (i.e. goes farther below the reset
threshold), the maximum allowable pulse width
decreases. Typically, a V_CC transient that goes
100mV below the reset threshold and lasts for
40µs or less will not cause a reset pulse to be
issued. A 100nF bypass capacitor mounted close
to the V pin provides additional transient
CC
immunity.
Applications
The SP706P/R/S/T-SP708R/S/T series offers
unmatched performance and the lowest power
consumption for these industry standard de-
vices. Refer to Figures 21 and 22 for supply
current performance characteristics rated against
temperature and supply voltages.
+3.3V/+3.0V
100kΩ
2N3904
MR
PFO
100kΩ
to µP
RESET
VCC
R1
PFI
R2
V-
GND
R1 ₌ VCC - 1.25 _{, VTRIP < 0}
R2 1.25 - VTRIP
+3.3V
MR
0V
V-
+3.3V
PFO
0V
V-
VTRIP
0V
Figure 18. Monitoring a Negative Voltage Supply
Buffered RESET connects to System Components
+3.3V/+3.0V
+3.3V/+3.0V
VCC
VCC
µP
RESET
RESET
4.7KΩ
GND
GND
Figure 19. Interfacing to Microprocessors with
Bidirectional RESET I/O for the SP706
Rev. 10-17-00
SP706 +3.0/ +3.3 Low Power Microprocessor Circuits
13
© Copyright 2000 Sipex Corporation