SP691A Datasheet, PDF (13/24 Pages) Sipex Corporation – Low Power Microprocessor Supervisory with Battery Switch-Over

OSC_SEL
OSC_IN
Watchdog Timeout Period
Normal
Immediately After Reset
LOW External Clock Input
1024 clocks
4096 clocks
LOW External Capacitor (600/47pF x C) ms
(2.4/4.7pf x C) sec
Floating
LOW
100 ms
1.6 s
Floating
Floating
1.6 s
1.6 s
Table 1. Reset Pulse Width and Watchdog Timeout Selections
Reset Timeout Period
2048 clocks
(1200/47pF x C) ms
200 ms
200 ms
RESET and RESET are asserted for the reset
timeout period (200ms nominal). WDO goes
to logic low and remains low until the next
transition at WDI. Refer to Figure 20. If WDI
is held high or low indefinitely, RESET and
RESET will generate 200ms pulses every 1.6s.
WDO has a 2 x TTL output characteristic.
The 10ns maximum CE propagation from CE_IN
to CE_OUT enables the SP691A/693A/800L/
800M devices to be used with most µPs.
Chip-Enable Input
CE_IN is in high impedance (disabled mode)
while RESET and/or RESET are asserted.
Selecting an Alternative Watchdog
Timeout Period
The OSC_SEL and OSC_IN inputs control the
watchdog are reset timeout periods. Floating
OSC_SEL and OSC_IN or tying them both to V_OUT
selects the nominal 1.6s watchdog timeout
period and 200ms reset timout period.
Connecting OSC to ground and floating or
IN
connecting OSC to V selects a 100ms nor-
SEL
OUT
mal watchdog timeout period and a 1.6s timeout
period immediately after reset. The reset timeout
period remains 200ms. Refer to Figure 20.
Select alternative timeout periods by connecting
OSC_SEL to ground and connecting a capacitor
between OSC_IN and ground, or by externally
driving OSC_IN . A synopsis of this control can
be found in Figure 21 and Table 1.
Chip-Enable Signal Gating
The SP691A/693A/800L/800M devices
provide internal gating of chip-enable (CE)
signals, to prevent erroneous data from
corrupting the CMOS RAM in the event of a
power failure. During normal operation, the CE
gate is enabled and passes all CE transitions.
When reset is asserted, this path becomes
disabled, preventing erroneous data from
corrupting the CMOS RAM. The SP691A/
693A/800L/800M devices use a series transmission
gate from CE_IN to CE_OUT. Refer to Figure 16.
During a power-down sequence where V_CC falls
below the reset threshold, CE_IN assumes a high
impedance state when the voltage at CE_IN goes
high or 12µs after RESET is asserted,
whichever occurs first. Refer to Figure 19.
During a power-up sequence, CE_IN remains high
impedance until RESET is deasserted.
In the high-impedance mode, the leakage
currents into CE_IN are <1µA over temperature.
In the low-impedance mode, the impedance of
CE_IN appears as a 65Ω resistor in series with
the load at CE_OUT.
The propagation delay through the CE
transmission gate depends on both the source
impedance of the drive to CE_IN and the
capacitive loading on CE (see the
OUT
Chip-Enable Propagation Delay vs. CE
OUT
Load Capacitance graph in the Typical
Performance Characteristics section). The
CE propagation delay is defined from the 50%
point on CE_IN to the 50% point on CE_OUT using
a 50Ω driver and 50pF of load capacitance as in
Figure 22. For minimum propagation delay,
minimize the capacitive load at CE_OUT and use
a low output-impedance driver.
Date: 5/25/04
SP691A/693A/800L/800M Low Power Microprocessor Supervisor with Battery Switch-Over © Copyright 2004 Sipex Corporation
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