SP6120 Datasheet, PDF (13/22 Pages) Sipex Corporation – Low Voltage, AnyFETTM, Synchronous ,Buck Controller Ideal for 2A to 10A, High Performance, DC-DC Power Converters

switch. It is during this interval that the 3%
window comparator has taken control away from
the main loop. The main loop regains control
only if the output voltage crosses through its
regulated value. Also notice where the 3%
comparator takes over. The output voltage is
considered “high” only if the trough of the ripple
is above 3%. The output voltage is considered
“low” only if the peak of the ripple is below 3%.
By managing the secondary loop in this fashion,
the SP6120 can improve the transient response
of high performance power converters without
causing strange disturbances in low to moderate
performance systems.
Driver Logic
Signals from the PWM latch (QPWM), Fault
latch (FAULT), Program Logic, Zero Crossing
Comparator, and 3% Window Comparators all
flow into the Driver Logic. The following is a
truth table for determining the state of the GH
and GL voltages for given inputs:
FAULT
QPWM or
3% COMP
NFET/PFET
DRIVER LOGIC TRUTH TABLE
1
1
0
0
0
0
0
0
0
0
X
X
1
1
0
0
0
0
0
0
N
P
N
P
N
P
N
P
N
P
CONT/DISC
X
X
X
X
C
C
D
D
D
D
ZERO CROSS
X
X
X
X
X
X
0
0
1
1
GH
0
1
1
0
0
1
0
1
0
1
GL
0
0
0
0
1
1
1
1
0
0
The QPWM and 3% Comparators are grouped
together because 3% Low is the same as QPWM
= 1 and 3% High is the same as QPWM = 0.
Output Drivers
The driver stage consists of one high side, 4Ω
driver, GH and one low side, 4Ω, NFET driver,
GL. As previously stated, the high side driver
can be configured to drive a PFET or an NFET
high side switch. The high side driver can also be
configured as a switch node referenced driver.
Due to voltage constraints, this mode is manda-
tory for 5V, single supply, high side NFET
applications. The following figure shows typical
THEORY OF OPERATIONS: Continued
driver waveforms for the 5V, high side NFET
design.
As with all synchronous designs, care must be
taken to ensure that the MOSFETs are properly
chosen for non-overlap time, peak current capa-
bility and efficiency.
5V
90%
GATE DRIVER TEST CONDITONS
GH (GL)
2V
10%
5V
FALL TIME
90%
GH (GL)
RISE TIME
2V
10%
V(BST)
NON-OVERLAP
GH
Voltage
0V
V(VCC)
GL
Voltage
0V
V(VCC = VIN)
SWN
Voltage
~0V
~V(Diode) V
~2V(VIN)
BST
Voltage
~V(VIN)
TIME
Date: 5/25/04
SP6120 Low Voltage, AnyFET^TM, Synchronous, Buck Controller
13
© Copyright 2004 Sipex Corporation