SP6832 Datasheet, PDF (12/15 Pages) Sipex Corporation – High Speed, High Efficiency Voltage Inverter

IN
2
+V_IN
OFF
ON
Shutdown
Logic
C1+
5
SP6832
GND
C1
4
C_IN
0.1µF
C1- ₃
1 ^OUT
V_OUT
C2
Figure 20. SP6832 Device with Shutdown Control
Combining a Doubler and Inverter Circuit
A designer can connect a SP6832 device in a
combination doubler/inverter circuit as seen in
Figure 19. The doubler uses capacitors C3 and
C4 while the inverter uses C1 and C2. Loading
either output decreases both output voltages to
GND because both the doubler and the inverter
circuits use the charge pump. Designers should
not allow the total current output from the
doubler and the inverter to exceed 40mA.
Connecting in Parallel
A designer can parallel a number of SP6832
devices to reduce the output resistance for
specific designs. All devices will need their own
flying capacitor, C1, but a single output capacitor
will serve all of the devices connected in
parallel by increasing the capacitance of C2 by
a factor of n where n equals the total number
of devices connected. This connection can be
found in Figure 21.
Implementing Shutdown
If shutdown control of the SP6832 devices is
necessary, the circuit found in Figure 20 can be
implemented. The 0.1µF capacitor at IN absorbs
transient input currents. The output resistance of
the devices can be determined by the following
equation:
R = 20 + 2 x R ,
OUT
BUFFER
where R_OUT is the output resistance and R_BUFFER
is the output resistance of the buffer driving IN.
R_BUFFER can be reduced by connecting multiple
buffers in parallel at IN. The polarity of the
SHUTDOWN signal can be changed by using a
noninverting buffer to drive IN.
Cascading Devices
A designer can cascade SP6832 devices to
produce a larger inverted voltage output. Refer
to Figure 22 for this circuit connection. With
two cascaded devices, the unloaded output
voltage is decreased by the output resistance of
the first device multiplied by the quiescent
current of the second device connected. The total
output resistance is greatly increased when
more than two devices are cascaded.
Layout and Grounding
Designers should make an effort to minimize
noise by paying special attention to the
circuit layout with the SP6832 devices.
External components should be connected in
close proximity to the device and a ground
plane should be implemented. This will keep
electrical traces short minimizing parasitic
inductance and capacitance.
SP6832DS/04
SP6832 High Speed, High Efficiency Voltage Inverter
12
© Copyright 2000 Sipex Corporation