SP3223E Datasheet, PDF (12/24 Pages) Sipex Corporation – Intelligent +3.0V to +5.5V RS-232 Transceivers

Receivers are active when the AUTO ON-LINE^®
circuitry is enabled or when in shutdown.
During the shutdown, the receivers will continue
to be active. If there is no activity present at the
receivers for a period longer than 100µs or when
SHUTDOWN is enabled, the device goes into a
standby mode where the circuit draws 1µA.
Driving EN to a logic HIGH forces the outputs of
the receivers into high-impedance. The truth
table logic of the SP3223E and SP3243E driver
and receiver outputs can be found in Table 2.
The SP3243E includes an additional non-invert-
ing receiver with an output R OUT. R OUT is an
2
2
extra output that remains active and monitors
activity while the other receiver outputs are
forced into high impedance. This allows Ring
Indicator (RI) from a peripheral to be monitored
without forward biasing the TTL/CMOS inputs
of the other devices connected to the receiver
outputs.
Since receiver input is usually from a transmis-
sion line where long cable lengths and system
interference can degrade the signal, the inputs
have a typical hysteresis margin of 300mV. This
ensures that the receiver is virtually immune to
noisy transmission lines. Should an input be left
unconnected, an internal 5KΩ pulldown resistor
to ground will commit the output of the receiver
to a HIGH state.
Charge Pump
The charge pump is a Sipex–patented design
(U.S. 5,306,954) and uses a unique approach
compared to older less–efficient designs. The
charge pump still requires four external
capacitors, but uses a four–phase voltage
shifting technique to attain symmetrical 5.5V
power supplies. The internal power supply
consists of a regulated dual charge pump that
provides output voltages 5.5V regardless of the
input voltage (V_CC) over the +3.0V to +5.5V
range. This is important to maintain compliant
RS-232 levels regardless of power supply
fluctuations.
The charge pump operates in a discontinuous
mode using an internal oscillator. If the output
voltages are less than a magnitude of 5.5V, the
charge pump is enabled. If the output voltages
exceed a magnitude of 5.5V, the charge pump is
disabled. This oscillator controls the four phases
of the voltage shifting. A description of each
phase follows.
Phase 1
— V_SS charge storage — During this phase of
the clock cycle, the positive side of capacitors
C₁ and C₂ are
then switched
transferred to
tCion₂^iG_–^{t.iaNlSlDyinaccnhedarCtgh}₂^e₊edcisthoacrVogn^Cen^Cie.nctCCed_1l+–
is
is
to
V_CC, the voltage potential across capacitor C₂ is
now 2 times V_CC.
Phase 2
— V_SS transfer — Phase two of the clock
connects the negative terminal of C₂ to the V_SS
storage capacitor and the positive terminal of C₂
to GND. This transfers a negative generated
voltage to C₃. This generated voltage is
regulated to a minimum voltage of -5.5V.
Simultaneous with the transfer of the voltage to
C₃, the positive side of capacitor C₁ is switched
to V_CC and the negative side is connected to
GND.
Phase 3
— V_DD charge storage — The third phase of the
clock is identical to the first phase — the charge
transferred in C₁ produces –V_CC in the negative
terminal of C₁, which
side of capacitor C₂.
is applied to the
Since C₂₊ is at
negative
V_CC, the
voltage potential across C₂ is 2 times V_CC.
Phase 4
— V_DD transfer — The fourth phase of the clock
connects the negative terminal of C₂ to GND,
and transfers this positive generated voltage
across C₂ to C₄, the V_DD storage capacitor. This
voltage is regulated to +5.5V. At this voltage,
the internal oscillator is disabled. Simultaneous
with the transfer of the voltage to C₄, the
positive side of capacitor C₁ is switched to V_CC
and the negative side is connected to GND,
allowing the charge pump cycle to begin again.
The charge pump cycle will continue as long as
the operational conditions for the internal
oscillator are present.
Rev. 11/14/02
SP3223E +3.0V to +5.5V RS-232 Transceivers
12
© Copyright 2002 Sipex Corporation