SP3223E_06 Datasheet, PDF (11/23 Pages) Sipex Corporation – Intelligent +3.0V to +5.5V RS-232 Transceivers

consists of a regulated dual charge pump that
provides output voltages 5.5V regardless of the
input voltage (V_CC) over the +3.0V to +5.5V
range. This is important to maintain compliant
RS-232 levels regardless of power supply
fluctuations.
The charge pump operates in a discontinuous
mode using an internal oscillator. If the output
voltages are less than a magnitude of 5.5V, the
charge pump is enabled. If the output voltages
exceed a magnitude of 5.5V, the charge pump is
disabled. This oscillator controls the four phases
of the voltage shifting. A description of each
phase follows.
Phase 1
— V_SS charge storage — During this phase of
the clock cycle, the positive side of capacitors
C₁ and C₂ are
then switched
transferred to
tCion₂^iG_–^{t.iaNlSlDyinaccnhedarCtgh}₂^e₊edcisthoacrVogn^Cen^Cie.nctCCed_1l+–
is
is
to
V_CC, the voltage potential across capacitor C₂ is
now 2 times V_CC.
voltage is regulated to +5.5V. At this voltage,
the internal oscillator is disabled. Simultaneous
with the transfer of the voltage to C₄, the
positive side of capacitor C₁ is switched to V_CC
and the negative side is connected to GND,
allowing the charge pump cycle to begin again.
The charge pump cycle will continue as long as
the operational conditions for the internal
oscillator are present.
Since both V⁺ and V^– are separately generated
from V_CC, in a no–load condition V⁺ and V^– will
be symmetrical. Older charge pump approaches
that generate V^– from V⁺ will show a decrease in
the magnitude of V^– compared to V⁺ due to the
inherent inefficiencies in the design.
AUTO ON-LINE^® Circuitry
The SP3223 devices have a patent pending
AUTO ON-LINE^® circuitry on board that saves
power in applications such as laptop computers,
PDA's, and other portable systems.
Phase 2
— V_SS transfer — Phase two of the clock
connects the negative terminal of C₂ to the V_SS
storage capacitor and the positive terminal of C₂
to GND. This transfers a negative generated
voltage to C₃. This generated voltage is
regulated to a minimum voltage of -5.5V.
Simultaneous with the transfer of the voltage to
C₃, the positive side of capacitor C₁ is switched
to V_CC and the negative side is connected to
GND.
Phase 3
— V_DD charge storage — The third phase of the
clock is identical to the first phase — the charge
transferred in C₁ produces –V_CC in the negative
terminal of C₁, which
side of capacitor C₂.
is applied to the
Since C₂₊ is at
negative
V_CC, the
voltage potential across C₂ is 2 times V_CC.
Phase 4
— V_DD transfer — The fourth phase of the clock
connects the negative terminal of C₂ to GND,
and transfers this positive generated voltage
across C₂ to C₄, the V_DD storage capacitor. This
The SP3223 devices incorporate an AUTO
ON-LINE^® circuit that automatically enables
itself when the external transmitters are enabled
and the cable is connected. Conversely, the
AUTO ON-LINE^® circuit also disables most of
the internal circuitry when the device is not being
used and goes into a standby mode where the
device typically draws 1µA. This function can
also be externally controlled by the ONLINE
pin. When this pin is tied to a logic LOW, the
AUTO ON-LINE^® function is active. Once
active, the device is enabled until there is no
activity on the receiver inputs. The receiver
input typically sees at least ±3V, which are
generated from the transmitters at the other end
of the cable with a ±5V minimum. When the
external transmitters are disabled or the cable is
disconnected, the receiver inputs will be pulled
down by their internal 5kΩ resistors to ground.
When this occurs over a period of time, the
internal transmitters will be disabled and the
device goes into a shutdown or standby mode.
When ONLINE is HIGH, the AUTO ON-LINE^®
mode is disabled.
Date: 10/06/06
SP3223 +3.0V to +5.5V RS-232 Transceivers
11
© Copyright 2006 Sipex Corporation