SP3220 Datasheet, PDF (11/16 Pages) Sipex Corporation – +3.0V to +5.5V RS-232 Driver/Receiver Pair

Phase 4
— V transfer — The fourth phase of the clock
DD
connects the negative terminal of C₂ to GND,
and transfers this positive generated voltage
across C to C , the V storage capacitor. This
2
4
DD
voltage is regulated to +5.5V. At this voltage,
the internal oscillator is disabled. Simultaneous
with the transfer of the voltage to C₄, the positive
side of capacitor C₁ is switched to V_CC and the
negative side is connected to GND, allowing the
charge pump cycle to begin again. The charge
pump cycle will continue as long as the
operational conditions for the internal oscillator
are present.
Since both V⁺ and V^– are separately generated
from V_CC; in a no–load condition V⁺ and V^– will
be symmetrical. Older charge pump approaches
that generate V^– from V⁺ will show a decrease in
the magnitude of V^– compared to V⁺ due to the
inherent inefficiencies in the design.
The clock rate for the charge pump typically
operates at 250kHz. The external capacitors can
be as low as 0.1µF with a 16V breakdown
voltage rating.
ESD Tolerance
The SP3220 device incorporates ruggedized
ESD cells on all driver output and receiver
input pins. The ESD structure is improved over
our previous family for more rugged applications
and environments sensitive to electro-static
discharges and associated transients.
The Human Body Model has been the generally
accepted ESD testing method for semiconductors.
This method is also specified in MIL-STD-883,
Method 3015.7 for ESD testing. The premise of
this ESD test is to simulate the human body’s
potential to store electro-static energy and
discharge it to an integrated circuit. The
simulation is performed by using a test model as
shown in Figure 14. This method will test the
IC’s capability to withstand an ESD transient
during normal handling such as in manufacturing
areas where the ICs tend to be handled
frequently.
For the Human Body Model, the current
limiting resistor (R_S) and the source capacitor
(C )
S
are
1.5kΩ
and
100pF,
respectively.
V_CC = +5V
+
C_{1 –}
–5V
+5V
+
C_{2 –}
–5V
Figure 9. Charge Pump — Phase 1
V_CC = +5V
+
C_{1 –}
Figure 10. Charge Pump — Phase 2
+
C_{2 –}
–10V
C₄
+ – _{VDD Storage Capacitor}
– + _{VSS Storage Capacitor}
C₃
C₄
+ – _{VDD Storage Capacitor}
– + _{VSS Storage Capacitor}
C₃
Rev. 6/25/03
SP3220 True +3.0 to +5.0V RS-232 Transceivers
11
© Copyright 2003 Sipex Corporation