SP3238E Datasheet, PDF (10/20 Pages) Sipex Corporation – Intelligent +3.0V to +5.5V RS-232 Transceivers

Since receiver input is usually from a transmission
line where long cable lengths and system
interference can degrade the signal, the inputs
have a typical hysteresis margin of 300mV. This
ensures that the receiver is virtually immune to
noisy transmission lines. Should an input be left
unconnected, an internal 5kΩ pulldown resistor
to ground will commit the output of the receiver
to a HIGH state.
Charge Pump
The charge pump is a Sipex–patented design
(U.S. 5,306,954) and uses a unique approach
compared to older less–efficient designs. The
charge pump still requires four external
capacitors, but uses a four–phase voltage
shifting technique to attain symmetrical 5.5V
power supplies. The internal power supply
consists of a regulated dual charge pump that
provides output voltages 5.5V regardless of the
input voltage (V_CC) over the +3.0V to +5.5V
range. This is important to maintain compliant
RS-232 levels regardless of power supply
fluctuations.
The charge pump operates in a discontinuous
mode using an internal oscillator. If the output
voltages are less than a magnitude of 5.5V, the
charge pump is enabled. If the output voltages
exceed a magnitude of 5.5V, the charge pump is
disabled. This oscillator controls the four phases
of the voltage shifting. A description of each
phase follows.
Phase 1
— V_SS charge storage — During this phase of
the clock cycle, the positive side of capacitors
C₁ and C₂ are
then switched
transferred to
tiCon₂^iGt_–^{i.aNSllDiynaccnehdaCrtgh}₂^e₊edicsthoacroVgn^Cen^Cie.nctCCed_1l+–
is
is
to
V_CC, the voltage potential across capacitor C₂ is
now 2 times V_CC.
Phase 2
— V_SS transfer — Phase two of the clock
connects the negative terminal of C₂ to the V_SS
storage capacitor and the positive terminal of C₂
to GND. This transfers a negative generated
voltage to C₃. This generated voltage is
regulated to a minimum voltage of -5.5V.
Simultaneous with the transfer of the voltage to
C₃, the positive side of capacitor C₁ is switched
to V_CC and the negative side is connected to
GND.
Phase 3
— V_DD charge storage — The third phase of the
clock is identical to the first phase — the charge
transferred in C₁ produces –V_CC in the negative
terminal of C₁, which
side of capacitor C₂.
is applied to the
Since C₂₊ is at
negative
V_CC, the
voltage potential across C₂ is 2 times V_CC.
Phase 4
— V_DD transfer — The fourth phase of the clock
connects the negative terminal of C₂ to GND,
and transfers this positive generated voltage
across C₂ to C₄, the V_DD storage capacitor. This
voltage is regulated to +5.5V. At this voltage,
the internal oscillator is disabled. Simultaneous
with the transfer of the voltage to C₄, the
positive side of capacitor C₁ is switched to V_CC
and the negative side is connected to GND,
allowing the charge pump cycle to begin again.
The charge pump cycle will continue as long as
the operational conditions for the internal
oscillator are present.
Since both V⁺ and V^– are separately generated
from V_CC, in a no–load condition V⁺ and V^– will
be symmetrical. Older charge pump approaches
that generate V^– from V⁺ will show a decrease in
the magnitude of V^– compared to V⁺ due to the
inherent inefficiencies in the design.
The clock rate for the charge pump typically
operates at 500kHz. The external capacitors can
be as low as 0.1µF with a 16V breakdown
voltage rating.
SP3238EDS/04
SP3238E +3.0V to +5.5V RS-232 Transceivers
10
© Copyright 1999 Sipex Corporation