SP3222EH_06 Datasheet, PDF (10/19 Pages) Sipex Corporation – 3.3V, 460 Kbps RS-232 Transceivers

Receivers
The receivers convert EIA/TIA-232 levels to
TTL or CMOS logic output levels. The
SP3222EH receivers have an inverting tri-state
output.Receiver outputs (RxOUT) are tri-stated
when the enable control EN = HIGH. In the
shutdown mode, the receivers can be active or
inactive. EN has no effect on TxOUT. The truth
table logic of the SP3222EH driver and receiver
outputs can be found in Table 2.
Since receiver input is usually from a transmis-
sion line where long cable lengths and system
interference can degrade the signal and inject
noise, the inputs have a typical hysteresis margin
of 300mV. Should an input be left unconnected,
a 5kΩ pulldown resistor to ground forces the
output of the receiver HIGH.
Charge Pump
The Sipex patented charge pump (5,306,954)
uses a four–phase voltage shifting technique to
attain symmetrical 5.5V power supplies and
requires four external capacitors. The internal
power supply consists of a regulated dual charge
pump that provides an output voltage of 5.5V
regardless of the input voltage (V_CC) over the
+3.0V to +5.5V range.
SHDN EN TxOUT RxOUT
0
0
Tri-state Active
0
1
Tri-state Tri-state
1
0
Active
Active
1
1
Active Tri-state
Table 2. Truth Table Logic for Shutdown and Enable
Control
In most circumstances, decoupling the power
supply can be achieved adequately using a
0.1µF bypass capacitor at C5 (refer to Figures 6
and7 ). In applications that are sensitive to
power-supply noise,V and ground can be
CC
decoupled with a capacitor of the same value
as charge-pump capacitor C1. It is always
important to physically locate bypass capacitors
close to the IC.
The charge pump operates in a discontinuous
mode using an internal oscillator. If the output
voltage is less than 5.5V, the charge pump is
enabled. If the output voltage exceeds 5.5V,
the charge pump is disabled. An oscillator
controls the four phases of the voltage shifting.
A description of each phase follows.
Phase 1: V_SSCharge Storage (Figure 12)
During this phase of the clock cycle, the positive
side of capacitors C₁ and C₂ are charged to V_CC.
C_l+ is then switched to GND and the charge in
C ^– is transferred to C ^–. Since C ⁺ is connected
1
2
2
to V_CC, the voltage potential across capacitor C₂
is now 2 times V_CC.
Phase 2: V_SSTransfer (Figure 13)
Phase two of the clock connects the negative
terminal of C₂ to the V_SS storage capacitor and
the positive terminal of C₂ to GND. This
transfers a negative generated voltage to C .
3
This generated voltage is regulated to a
minimum voltage of -5.5V. Simultaneous with
the transfer of the voltage to C , the positive side
3
of capacitor C₁ is switched to V_CC and the
negative side is connected to GND.
Phase 3: V Charge Storage
DD
(Figure 15)
The third phase of the clock is identical to the
first phase — the charge transferred in C₁
produces –V_CC in the negative terminal of C₁,
which is applied to the negative side of capacitor
C₂. Since C₂₊ is at V_CC, the voltage potential
across C is 2 times V .
2
CC
Date: 1/18/06
SP3222EH/3232EH 3.3V, 460 Kbps RS-232 Transceivers
10
© Copyright 2006 Sipex Corporation