SP3222B Datasheet, PDF (10/18 Pages) Sipex Corporation – True +3.0V to +5.5V RS-232 Transceivers

Receivers
The receivers convert EIA/TIA-232 levels to
TTL or CMOS logic output levels. The SP3222B
receivers have an inverting tri-state output. These
receiver outputs (RxOUT) are tri-stated when
the enable control EN = HIGH. In the shutdown
mode, the receivers can be active or inactive.
EN has no effect on TxOUT. The truth table
logic of the SP3222B driver and receiver out-
puts can be found in Table 2.
Since receiver input is usually from a transmis-
sion line where long cable lengths and system
interference can degrade the signal, the inputs
have a typical hysteresis margin of 300mV. This
ensures that the receiver is virtually immune to
noisy transmission lines. Should an input be left
unconnected, a 5kΩ pulldown resistor to ground
will commit the output of the receiver to a HIGH
state.
Charge Pump
The charge pump is a Sipex–patented design
(5,306,954) and uses a unique approach com-
pared to older less–efficient designs. The charge
pump still requires four external capacitors, but
uses a four–phase voltage shifting technique to
attain symmetrical 5.5V power supplies. The
internal power supply consists of a regulated
dual charge pump that provides output voltages
5.5V regardless of the input voltage (V_CC) over
the +3.0V to +5.5V range.
In most circumstances, decoupling the power
supply can be achieved adequately using a 0.1µF
bypass capacitor at C5 (refer to Figures 8 and 9).
SHDN EN TxOUT RxOUT
0
0
Tri-state Active
0
1
Tri-state Tri-state
1
0
Active
Active
1
1
Active Tri-state
Table 2. SP3222B Truth Table Logic for Shutdown and
Enable Control
In applications that are sensitive to power-sup-
ply noise, decouple V to ground with a capaci-
CC
tor of the same value as charge-pump capacitor
C1. Physically connect bypass capacitors as
close to the IC as possible.
The charge pumps operate in a discontinuous
mode using an internal oscillator. If the output
voltages are less than a magnitude of 5.5V, the
charge pumps are enabled. If the output voltage
exceed a magnitude of 5.5V, the charge pumps
are disabled. This oscillator controls the four
phases of the voltage shifting. A description of
each phase follows.
Phase 1
— V_SS charge storage — During this phase of
the clock cycle, the positive side of capacitors
C₁ and C₂ are initially charged to V_CC. C_l+ is
then switched to GND and the charge in C_1– is
transferred to C_2–. Since C₂₊ is connected to
V_CC, the voltage potential across capacitor C₂
is now 2 times V .
CC
Phase 2
— V transfer — Phase two of the clock con-
SS
nects the negative terminal of C₂ to the V_SS
storage capacitor and the positive terminal of C₂
to GND. This transfers a negative generated
voltage to C₃. This generated voltage is regu-
lated to a minimum voltage of -5.5V. Simulta-
neous with the transfer of the voltage to C₃, the
positive side of capacitor C₁ is switched to V_CC
and the negative side is connected to GND.
Phase 3
— V_DD charge storage — The third phase of the
clock is identical to the first phase — the charge
transferred in C₁ produces –V_CC in the negative
terminal of C₁, which is applied to the negative
side of capacitor C₂. Since C₂₊ is at V_CC, the
voltage potential across C₂ is 2 times V_CC.
Phase 4
— V_DD transfer — The fourth phase of the clock
connects the negative terminal of C₂ to GND,
and transfers this positive generated voltage
across C₂ to C₄, the V_DD storage capacitor.
Rev. 6/30/03
SP3222B/3232B True +3.0 to +5.5V RS-232 Transceivers
10
© Copyright 2003 Sipex Corporation