SP3203E Datasheet, PDF (10/16 Pages) Sipex Corporation – 3V RS-232 Serial Transceiver with Logic Selector and15kV ESD Protection

duces –V_CC in the negative terminal of C₁, which
is applied
Since C₂₊
to the negative side of capacitor C₂.
is at V_CC, the voltage potential across
C₂ is 2 times V_CC.
V Transfer-Phase 4 (Figure 16)
DD
The fourth phase of the clock connects the nega-
tive terminal of C₂ to GND, and transfers this
positive generated voltage across C₂ to C₄, the
V_DD storage capacitor. This voltage is regulated
to +5.5V. At this voltage, the internal oscillator
is disabled. Simultaneous with the transfer of the
voltage to C₄, positive side of capacitor C₁ is
switched to V_CC and the negative side is con-
nected to GND, allowing the charge pump cycle
to begin again. The charge pump cycle will
continue as long as the operational conditions for
the internal oscillator are present.
Since both V⁺ and V^– are separately generated
from V_CC, in a no–load condition, V⁺ and V^– will
be symmetrical. Older charge pump approaches
that generate V^– from V⁺ will show a decrease in
the magnitude of V^– compared to V⁺ due to the
inherent ineffiencies in the design.
The clock rate for the charge pump is typically
operates at 250kHz. The external capacitors are
usually 0.1µF with a 16V breakdown voltage
rating.
V_L Supply Level
Current RS-232 serial tranceivers are designed
with fixed 5V or 3.3V TTL input/output voltages
levels. The V_L function in the SP3203E allows
the end user to set the TTL input/output voltage
levels independent of V_CC. By connecting V_L to
the main logic bus of system, the TTL input/
output limits and threshold are reset to interface
with the on board low voltage logic circuity.
Capacitor Selection Table:
V_CC (V)
3.0 to 3.6
C1 (µF)
0.1
C2-C4(µF)
0.1
4.5 to 5.5
0.047
0.33
3.0 to 5.5
0.22
1
Rev. 2/7/01
SP3203E
10
© Copyright 2001 Sipex Corporation