SP4306 Datasheet, PDF (5/10 Pages) SIPAT Co,Ltd – 50 Ω RF Digital Attenuator

SP4306
Product Specification
Figure 14. Pin Configuration (Top View)
C16 1
RF1 2
Data 3
Clock 4
LE 5
20-lead
QFN
4x4 mm
Exposed Solder Pad
15 C8
14 RF2
13 P/S
12 Vss/GND
11 GND
Table 3. Absolute Maximum Ratings
Symbol Parameter/Conditions Min Max Units
V_DD
Power supply voltage
-0.3 4.0
V
V_I
Voltage on any DC input
-0.3
V_DD+
0.3
V
T_ST
Storage temperature range -65 150
°C
PIN
V_ESD
Input power (50Ω)
ESD voltage (Human Body
Model)
+30 dBm
500
V
Exceeding absolute maximum ratings may cause per-
manent damage. Operation should be restricted to the
limits in the Operating Ranges table. Operation be-
tween operating range maximum and absolute maxi-
mum for extended periods may reduce reliability.
Table 2. Pin Descriptions
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Paddle
Pin
Name
C16
RF1
Data
Clock
LE
V_DD
PUP1
PUP2
V_DD
GND
GND
V_ss/GND
P/S
RF2
C8
C4
C2
GND
C1
N/C
GND
Description
Attenuation control bit, 16 dB (Note 4).
RF port (Note 1).
Serial interface data input (Note 4).
Serial interface clock input.
Latch Enable input (Note 2).
Power supply pin.
Power-up selection bit.
Power-up selection bit.
Power supply pin.
Ground connection.
Ground connection.
Negative supply voltage or GND connection
(Note 3)
Parallel/Serial mode select.
RF port (Note 1).
Attenuation control bit, 8 dB.
Attenuation control bit, 4 dB.
Attenuation control bit, 2 dB.
Ground connection.
Attenuation control bit, 1 dB.
No connect. Can be connected to any bias.
Ground for proper operation
Notes: 1: Both RF ports must be held at 0 V_DC or DC blocked with an
external series capacitor.
2: Latch Enable (LE) has an internal 100 kΩresistor to V_DD.
3: Connect pin 12 to GND to enable internal negative voltage
generator. Connect pin 12 to V_SS (-VDD) to bypass and
disable internal negative voltage generator.
4. Place a 10 kΩresistor in series, as close to pin as possible
to avoid frequency resonance. See “Resistor on Pin 1 & 3”
paragraph
Table 4. Operating Ranges
Parameter
V_DD Power Supply
Voltage
I_DD Power Supply
Current
Digital Input High
Digital Input Low
Digital Input Leakage
Min Typ Max Units
2.7
3.0
3.3
V
0.7xV_DD
100
µA
V
0.3xV_DD
V
1
µA
Input Power
+24
dBm
Temperature range
-40
85
°C
Exposed Solder Pad Connection
The exposed solder pad on the bottom of the package
must be grounded for proper device operation.
Electrostatic Discharge (ESD) Precautions
When handling this CMOS device, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rate specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, CMOS de-
vices are immune to latch-up.
Switching Frequency
The SP4306 has a maximum 25 kHz switching rate.
Resistor on Pin 1 & 3
A 10 kΩ resistor on the inputs to Pin 1 & 3 (see Figure
16) will eliminate package resonance between the RF
input pin and the two digital inputs. Specified
attenuation error versus frequency performance is
dependent upon this condition.
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