SP4272 Datasheet, PDF (4/10 Pages) SIPAT Co,Ltd – SPDT Broadband CMOS

SP4272
Product Specification
Evaluation Kit
The SPDT Switch Evaluation Kit board was
designed to ease customer evaluation of the
SP4272 SPDT switch. The RF common port is
connected through a 75 Ω transmission line to the
bottom F connector, J2. Port 1 and Port 2 are
connected through 75 Ω transmission lines to two F
connectors on either side of the board, J1 and J3. A
through transmission line connects F connectors J4
and J5. This transmission line can be used to
estimate the loss of the PCB over the environmental
conditions being evaluated.
The board is constructed of a two metal layer FR4
material with a total thickness of 0.031”. The bottom
layer provides ground for the RF transmission lines.
The transmission lines were designed using a
coplanar waveguide with ground plane model using
a trace width of 0.021”, trace gaps of 0.030”,
dielectric thickness of 0.028”, copper thickness of
0.0021” and ε_r of 4.3.
J6 provides a means for controlling the DC inputs to
the device. The lower right pin (J6-2) is connected
to the device CTRL input. The upper right pin (J6-1)
is connected to the device V_DD input. Footprints for
decoupling capacitors are provided on both CTRL
and V_DD traces. It is the responsibility of the
customer to determine proper supply decoupling for
their design application. Removing these
components from the evaluation board has not been
shown to degrade RF performance.
Figure 4. Evaluation Board Layouts
Figure 5. Evaluation Board Schematic
Tel: [phone]
Page 4 of 10
Fax: [phone]
DD
www.sipatsaw.com / [e-mail]