SP4257 Datasheet, PDF (4/6 Pages) SIPAT Co,Ltd – 50 Ω SPDT Absorptive CMOS

SP4257
Product Specification
Evaluation Kit
The SPDT Switch Evaluation Kit board was designed to
ease customer evaluation of the SP4257 SPDT switch.
The RF common port is connected through a 50 Ω
transmission line to J2. Port 1 and Port 2 are
connected through 50 Ω transmission lines to J1 and
J3. A through transmission line connects SMA
connectors J4 and J5. This transmission line can be
used to estimate the loss of the PCB over the
environmental conditions being evaluated.
The board is constructed of a four metal layer FR4
material with a total thickness of 0.031”. The
transmission lines were designed using a coplanar
waveguide with ground plane (28 mil core, 47.6 mil
width, 30mil gap).
Note the number of vias surrounding the device in the
layout shown in Figure 8. These vias are critical for
obtaining the specified isolation performance for the
device shown in this datasheet.
J6 provides a means for controlling DC and digital
inputs to the device. The provided jumpers short the
package pin to ground for logic low. When the jumper
is removed, the pin is pulled up to VDD for logic high.
When the jumper is in place, 3 µA of current will flow
through the 1 MΩ pull up resistor. This extra current
should not be attributed to the requirements of the
device.
Figure 8. Evaluation Board Layouts
Figure 9. Evaluation Board Schematic
C1
R1
DNI
1M
J6
HEADER 7X2
11
33
55
77
99
11 ₁₁
13 ₁₃
22
44
66
88
10 ¹⁰
12 ¹²
14 ¹⁴
R2
1M
J1
1
50 OHM T-Line
1 _GND
GND ¹⁵
2 _GND
GND ¹⁴
3
RF1
U1
PE4255/PE4257/PE42551
RF2 ¹³
4 _GND
GND ¹²
5 _GND
GND ¹¹
C2
C3
DNI
DNI
50 OHM T-Line
J3
1
J2
1
50 OHM T-Line
J4
1
50 OHM T-Line
J5
1
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