SP4307 Datasheet, PDF (2/10 Pages) SIPAT Co,Ltd – 75 Ω RF Digital Attenuator

SP4307
Product Specification
Figure 15. Pin Configuration (Top View)
N/C 1
RF1 2
Data 3
Clock 4
LE 5
20-lead
QFN
4x4mm
Exposed Solder Pad
15 C8
14 RF2
13 P/S
12 Vss/GND
11 GND
Table 2. Pin Descriptions
Pin
Pin
No.
Name
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Paddle
N/C
RF1
Data
Clock
LE
VDD
N/C
PUP2
VDD
GND
GND
Vss/GND
P/S
RF2
C8
C4
C2
GND
C1
C0.5
GND
No connect
RF port (Note 1).
Serial interface data input (Note 4).
Serial interface clock input.
Latch Enable input (Note 2).
Power supply pin.
No connect
Power-up selection bit.
Power supply pin.
Ground connection.
Ground connection.
Negative supply voltage or GND
connection(Note 3)
Parallel/Serial mode select.
RF port (Note 1).
Attenuation control bit, 8 dB.
Attenuation control bit, 4 dB.
Attenuation control bit, 2 dB.
Ground connection.
Attenuation control bit, 1 dB.
Attenuation control bit, 0.5 dB.
Ground for proper operation
Notes: 1: Both RF ports must be held at 0 VDC or DC blocked with an
external series capacitor.
2: Latch Enable (LE) has an internal 100 kΩresistor to VDD.
3: Connect pin 12 to GND to enable internal negative voltage
generator. Connect pin 12 to VSS (-VDD) to bypass and
disable internal negative voltage generator.
4. Place a 10 kΩresistor in series, as close to pin as possible
to avoid frequency resonance. See “Resistor on 3”
paragraph
Table 3. Absolute Maximum Ratings
Symbol Parameter/Conditions Min Max Units
VDD
Power supply voltage
-0.3 4.0
V
VI
Voltage on any input
-0.3
VDD+
0.3
V
TST
Storage temperature range -65 150
°C
PIN
Input power (50Ω)
VESD
ESD voltage (Human Body
Model)
+30 dBm
500
V
Table 4. Operating Ranges
Parameter
VDD Power Supply
Voltage
IDD Power Supply
Current
Digital Input High
Min Typ
2.7
3.0
0.7xVDD
Digital Input Low
Digital Input Leakage
Max
3.3
100
0.3xVDD
1
Units
V
µA
V
V
µA
Input Power
Temperature range
-40
+24
dBm
85
°C
Exposed Solder Pad Connection
The exposed solder pad on the bottom of the
package must be grounded for proper device
operation.
Electrostatic Discharge (ESD) Precautions
When handling this CMOS device, observe
the same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rate specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices,CMOS
devices are immune to latch-up.
Switching Frequency
The SP4307 has a maximum 25 kHz switching rate.
Resistor on Pin 3
A 10 kΩ resistor on the input to Pin 3 (see Figure 5)
will eliminate package resonance between the RF
input pin and the digital input. Specified attenuation
error versus frequency performance is dependent
upon this condition.
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