STK15C88_08 Datasheet, PDF(8/15 Page) Simtek Corporation

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STK15C88_08 Datasheet, PDF (8/15 Pages) Simtek Corporation – 32Kx8 PowerStore nvSRAM

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STK15C88

nvSRAM OPERATION

The STK15C88 is a versatile memory chip that pro-

vides several modes of operation. The STK15C88

can operate as a standard 32K x 8 SRAM. It has a

32K x 8 nonvolatile element shadow to which the

SRAM information can be copied, or from which the

SRAM can be updated in nonvolatile mode.

NOISE CONSIDERATIONS

Note that the STK15C88 is a high-speed memory

and so must have a high-frequency bypass capaci-

tor of approximately 0.1Î¼F connected between VCC

and VSS, using leads and traces that are as short as

possible. As with all high-speed CMOS ICs, normal

careful routing of power, ground and signals will help

prevent noise problems.

SRAM READ

The STK15C88 performs a READ cycle whenever E

and G are low and W is high. The address specified

on pins A0-14 determines which of the 32,768 data

bytes will be accessed. When the READ is initiated

by an address transition, the outputs will be valid

after a delay of tAVQV (READ cycle #1). If the READ is

initiated by E or G, the outputs will be valid at tELQV or

at tGLQV, whichever is later (READ cycle #2). The data

outputs will repeatedly respond to address changes

within the tAVQV access time without the need for tran-

sitions on any control input pins, and will remain valid

until another address change or until E or G is

brought high.

SRAM WRITE

A WRITE cycle is performed whenever E and W are

low. The address inputs must be stable prior to

entering the WRITE cycle and must remain stable

until either E or W goes high at the end of the cycle.

The data on the common I/O pins DQ0-7 will be writ-

ten into the memory if it is valid tDVWH before the end

of a W controlled WRITE or tDVEH before the end of an

E controlled WRITE.

It is recommended that G be kept high during the

entire WRITE cycle to avoid data bus contention on

the common I/O lines. If G is left low, internal cir-

cuitry will turn off the output buffers tWLQZ after W

goes low.

SOFTWARE NONVOLATILE STORE

The STK15C88 software STORE cycle is initiated by

executing sequential READ cycles from six specific

address locations. During the STORE cycle an erase

of the previous nonvolatile data is first performed,

followed by a program of the nonvolatile elements.

The program operation copies the SRAM data into

nonvolatile memory. Once a STORE cycle is initi-

ated, further input and output are disabled until the

cycle is completed.

Because a sequence of READs from specific

addresses is used for STORE initiation, it is impor-

tant that no other READ or WRITE accesses inter-

vene in the sequence or the sequence will be

aborted and no STORE or RECALL will take place.

To initiate the software STORE cycle, the following

READ sequence must be performed:

1. Read address

2. Read address

3. Read address

4. Read address

5. Read address

6. Read address

0E38 (hex)

31C7 (hex)

03E0 (hex)

3C1F (hex)

303F (hex)

0FC0 (hex)

Valid READ

Initiate STORE cycle

The software sequence must be clocked with E con-

trolled READs.

Once the sixth address in the sequence has been

entered, the STORE cycle will commence and the

chip will be disabled. It is important that READ cycles

and not WRITE cycles be used in the sequence,

although it is not necessary that G be low for the

sequence to be valid. After the tSTORE cycle time has

been fulfilled, the SRAM will again be activated for

READ and WRITE operation.

SOFTWARE NONVOLATILE RECALL

A software RECALL cycle is initiated with a sequence

of READ operations in a manner similar to the soft-

ware STORE initiation. To initiate the RECALL cycle,

the following sequence of READ operations must be

performed: