STK17TA8_08 Datasheet, PDF (6/29 Pages) Simtek Corporation – 128Kx8 Autostore nvSRAM With Real-Time Clock

STK17TA8
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
#1
#2
Alt.
PARAMETER
1
2
t_AVAVc
3
t_AVQVd
4
5
t_AXQXd
6
7
t_ELQV
t_ELEHc
t_AVQVd
t_GLQV
t_AXQXd
t_ELQX
t_EHQZe
t_ACS
Chip Enable Access Time
t_RC
Read Cycle Time
t_AA
Address Access Time
t_OE
Output Enable to Data Valid
t_OH
Output Hold after Address Change
t_LZ
Address Change or Chip Enable to
Output Active
t_HZ
Address Change or Chip Disable to
Output Inactive
8
t_GLQX
t_OLZ
Output Enable to Output Active
9
t_GHQZe
t_OHZ
Output Disable to Output Inactive
10
t_ELICCLb
t_PA
Chip Enable to Power Active
11
t_EHICCHb
t_PS
Chip Disable to Power Standby
Note c:
Note d:
Note e:
Note f:
W must be high during SRAM READ cycles.
Device is continuously selected with E and G both low
Measured ± 200mV from steady state output voltage.
HSB must remain high during READ and WRITE cycles.
STK17TA8-25
MIN MAX
25
25
25
12
3
STK17TA8-45
MIN MAX
45
45
45
20
3
UNITS
ns
ns
ns
ns
ns
3
3
ns
10
15
ns
0
0
ns
10
15
ns
0
0
ns
25
45
ns
SRAM READ CYCLE #1: Address Controlled^c,d,f
ADDRESS
DQ (DATA OUT)
5
t_AXQX
2
t_AVAV
3
t_AVQV
SRAM READ CYCLE #2: E and G Controlled^c,f
ADDR ESS
E
27
G
DQ (DATA OUT)
ICC
6
t_{ELQ X}
2
t_{E LE H}
1
t_{EL Q V}
3
t_{AV QV}
8
tG L Q X
4
t_{G L QV}
10
tELI CC H
ST AND BY
AC T IVE
DATA VALID
29
tEHAX
11
tEHI CC L
7
tEHQ Z
9
tGH Q Z
DAT A VAL ID
Document Control #ML0025 Rev 2.0
6
Jan, 2008