STK14EC16 Datasheet, PDF (6/21 Pages) Simtek Corporation – 256Kx16 AutoStore nvSRAM

STK14EC16
Preliminary
SRAM READ CYCLES #1 & #2
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
#1
t_AVAVc
t_AVQVd
t_AXQXd
SYMBOLS
#2
t_ELQV
t_ELEHc
t_AVQVd
t_GLQV
t_BLQV
t_AXQXd
t_ELQX
t_EHQZe
t_BLQX
t_GLQX
t_GHQZe
t_BHQZe
t_ELICCHb
t_EHICCLb
Alt.
t_ACS
t_RC
t_AA
t_OE
t_OH
t_LZ
t_HZ
t_OLZ
t_OHZ
t_PA
t_PS
PARAMETER
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Byte Enable to Data Valid
Output Hold after Address Change
Address Change or Chip Enable to
Output Active
Address Change or Chip Disable to
Output Inactive
Byte Enable to Output Active
Output Enable to Output Active
Output Disable to Output Inactive
Byte Enable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
STK14EC16-15
MIN MAX
15
15
15
10
10
3
STK14EC16-25
MIN MAX
25
25
25
12
12
3
STK14EC16-45
MIN MAX
45
45
45
20
20
3
UNITS
ns
ns
ns
ns
ns
ns
3
3
3
ns
7
10
15
ns
7
10
15
ns
0
0
0
ns
7
10
15
ns
7
10
15
ns
0
0
0
ns
15
25
45
ns
Note c:
Note d:
Note e:
Note f:
W must be high during SRAM READ cycles.
Device is continuously selected with E and G both low, LB and UB select bytes read.
Measured ± 200mV from steady state output voltage.
HSB must remain high during READ and WRITE cycles.
SRAM READ CYCLE #1: Address Controlled^c,d,f
t_AVAV (2)
Address
Address Valid
t_AVQV (3)
Data Output
Previous Data Valid
t_{AXQX (6)}
Output Data Valid
SRAM READ CYCLE #2: E and G Controlled^c,f
ADDR ESS
E
27
G
DQ (D ATA OUT)
ICC
6
t_{ELQ X}
2
t_{E LE H}
1
t_{EL Q V}
3
t_{AV QV}
8
tG L Q X
4
t_{G L QV}
10
tELI CC H
ST AND BY
AC T IVE
Document Control #ML0061 Rev 1.1
6
Jan, 2008
Simtek Confidential
29
tEHAX
11
tEHI CC L
7
tEHQ Z
9
tGH Q Z
DAT A VAL ID