STK22C48_08 Datasheet, PDF (4/16 Pages) Simtek Corporation – 2Kx8 AutoStore nvSRAM

STK22C48
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
#1, #2
Alt.
PARAMETER
1
t_ELQV
2
t_AVAVg, t_ELEHg
3
t_AVQVh
4
t_GLQV
5
t_AXQXh
6
t_ELQX
7
t_EHQZi
8
t_GLQX
9
t_GHQZi
10
t_ELICCHf
11
t_EHICCLf
t_ACS
t_RC
t_AA
t_OE
t_OH
t_LZ
t_HZ
t_OLZ
t_OHZ
t_PA
t_PS
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Address Change or Chip Enable to Output Active
Address Change or Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
Note g: W and HSB must be high during SRAM READ cycles.
Note h: Device is continuously selected with E and G both low.
Note i: Measured ± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlled^{g, h}
(V_CC = 5.0V ± 10%)^e
STK22C48-25
MIN MAX
STK22C48-45
MIN MAX
UNITS
25
45
ns
25
45
ns
25
45
ns
10
20
ns
5
5
ns
5
5
ns
10
15
ns
0
0
ns
10
15
ns
0
0
ns
25
45
ns
ADDRESS
DQ (DATA OUT)
5
t_AXQX
2
t_AVAV
3
t_AVQV
DATA VALID
SRAM READ CYCLE #2: E and G Controlled^g
ADDR ESS
E
27
6
t_{ELQ X}
2
t_{E LE H}
1
t_{EL Q V}
G
DQ (D ATA OUT)
ICC
3
t_{AV QV}
8
tG L Q X
4
t_{G L QV}
10
tELI CC H
ST AND BY
AC T IVE
29
tEHAX
11
tEHI CC L
7
tEHQ Z
9
tGH Q Z
DAT A VAL ID
Document Control #ML0004 Rev 2.0
4
Feb, 2008