STK16C88 Datasheet, PDF (4/12 Pages) List of Unclassifed Manufacturers – 32K x 8 AutoStorePlus nvSRAM QuantumTrap CMOS Nonvolatile Static RAM

STK16C88
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
#1, #2
Alt.
PARAMETER
1
t_ELQV
2
t_AVAV^f
3
t_AVQV^g
t_ACS
t_RC
t_AA
4
t_GLQV
t_OE
5
t_AXQX^g
t_OH
6
t_ELQX
t_LZ
7
t_EHQZ^h
t_HZ
8
t_GLQX
t_OLZ
9
t_GHQZ^h
t_OHZ
10
t_ELICCH^e
t_PA
11
t_EHICCL^{d, e}
t_PS
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note g: I/O state assumes E, G < V_IL and W > V_IH; device is continuously selected.
Note h: Measured + 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlled^{f, g}
ADDRESS
DQ (DATA OUT)
5
t_AXQX
2
t_AVAV
3
t_AVQV
SRAM READ CYCLE #2: E Controlled^f
ADDRESS
E
6
t_ELQX
2
t_AVAV
1
t_ELQV
DATA VALID
(V_CC = 5.0V ± 10%)
STK16C88-25 STK16C88-45
UNITS
MIN MAX MIN MAX
25
45
ns
25
45
ns
25
45
ns
10
20
ns
5
5
ns
5
5
ns
10
15
ns
0
0
ns
10
15
ns
0
0
ns
25
45
ns
11
t_EHICCL
7
t_EHQZ
G
DQ (DATA OUT)
I_CC
4
8 ^tGLQV
t_GLQX
10
t_ELICCH
STANDBY
ACTIVE
9
t_GHQZ
DATA VALID
Document Control #ML0018 Rev 0.3
4
February, 2007