STK17TA8 Datasheet, PDF (13/28 Pages) List of Unclassifed Manufacturers – nvTime™ Event Data Recorder 128K x 8 AutoStore™ nvSRAM with Real-Time Clock Product Preview

STK17TA8
has taken place. The HSB signal can be monitored
by the system to detect an AutoStore cycle is in
progress.
HARDWARE STORE (HSB) OPERATION
The STK17TA8 provides the HSB pin for controlling
and acknowledging the STORE operations. The
HSB pin can be used to request a hardware STORE
cycle. When the HSB pin is driven low, the
STK17TA8 will conditionally initiate a STORE opera-
tion after t_DELAY. An actual STORE cycle will only
begin if a WRITE to the SRAM took place since the
last STORE or RECALL cycle. The HSB pin also
acts as an open drain driver that is internally driven
low to indicate a busy condition while the STORE
(initiated by any means) is in progress. This pin
should be externally pulled up if it is used to drive
other inputs.
SRAM READ and WRITE operations that are in
progress when HSB is driven low by any means are
given time to complete before the STORE operation
is initiated. After HSB goes low, the STK17TA8 will
continue to allow SRAM operations for t_DELAY. Dur-
ing t_DELAY, multiple SRAM READ operations may
take place. If a WRITE is in progress when HSB is
pulled low, it will be allowed a time, t_DELAY, to com-
plete. However, any SRAM WRITE cycles
requested after HSB goes low will be inhibited until
HSB returns high.
If HSB is not used, it should be left unconnected.
HARDWARE RECALL (POWER-UP)
During power up or after any low-power condition
(V_CC<V_SWITCH), an internal RECALL request will be
latched. When V_CC once again exceeds the sense
voltage of V_SWITCH, a RECALL cycle will automati-
cally be initiated and will take t_HRECALL to complete.
SOFTWARE STORE
Data can be transferred from the SRAM to the non-
volatile memory by a software address sequence.
The STK17TA8 software STORE cycle is initiated by
executing sequential E controlled or G controlled
READ cycles from six specific address locations in
exact order. During the STORE cycle, previous data
is erased and then the new data is programmed into
the nonvolatile elements. Once a STORE cycle is
initiated, further memory inputs and outputs are dis-
abled until the cycle is completed.
To initiate the software STORE cycle, the following
READ sequence must be performed:
1 Read Address
2 Read Address
3 Read Address
4 Read Address
5 Read Address
6 Read Address
0x4E38 Valid READ
0xB1C7 Valid READ
0x83E0 Valid READ
0x7C1F Valid READ
0x703F Valid READ
0x8FC0 Initiate STORE Cycle
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ
cycles and not WRITE cycles be used in the
sequence and that G is active. After the t_STORE
cycle time has been fulfilled, the SRAM will again be
activated for READ and WRITE operation.
SOFTWARE RECALL
Data can be transferred from the nonvolatile mem-
ory to the SRAM by a software address sequence. A
software RECALL cycle is initiated with a sequence
of READ operations in a manner similar to the soft-
ware STORE initiation. To initiate the RECALL
cycle, the following sequence of E controlled or G
controlled READ operations must be performed:
1 Read Address
2 Read Address
3 Read Address
4 Read Address
5 Read Address
6 Read Address
0x4E38 Valid READ
0xB1C7 Valid READ
0x83E0 Valid READ
0x7C1F Valid READ
0x703F Valid READ
0x4C63 Initiate RECALL Cycle
Internally, RECALL is a two-step procedure. First,
the SRAM data is cleared, and second, the nonvola-
tile information is transferred into the SRAM cells.
After the t_RECALL cycle time, the SRAM will once
again be ready for READ or WRITE operations. The
RECALL operation in no way alters the data in the
nonvolatile storage elements.
Document Control #ML0025 Rev 1.5
13
March 2007