UL634H256 Datasheet, PDF (1/15 Pages) List of Unclassifed Manufacturers – LOW VOLTAGE POWERSTORE 32K X 8 NVSRAM

Not Recommended For New Designs
UL634H256
Low Voltage PowerStore 32K x 8 nvSRAM
Features
Description
‡ High-performance CMOS non- The UL634H256 has two separate
volatile static RAM 32768 x 8 bits modes of operation: SRAM mode
‡ 35 and 45 ns Access Times
and nonvolatile mode. In SRAM
‡ 15 and 20 ns Output Enable
mode, the memory operates as an
Access Times
‡ I_CC = 8 mA typ. at 200 ns Cycle
Time
‡ Automatic STORE to EEPROM
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
on Power Down using external mode SRAM functions are disab-
capacitor
‡ Software initiated STORE
‡ Automatic STORE Timing
‡ 10⁶ STORE cycles to EEPROM
‡ 100 years data retention in
led.
The UL634H256 is a fast static
RAM (35 and 45 ns), with a nonvo-
latile electrically erasable PROM
(EEPROM) element incorporated
EEPROM
in each static memory cell. The
‡ Automatic RECALL on Power Up SRAM can be read and written an
‡ Software RECALL Initiation
unlimited number of times, while
‡ Unlimited RECALL cycles from independent nonvolatile data resi-
EEPROM
des in EEPROM.
‡ Wide voltage range: 2.7 ... 3.6 V Data transfers from the SRAM to
(3.0 ... 3.6 V for 35 ns type)
‡ Operating temperature range:
the EEPROM (the STORE opera-
tion) take place automatically upon
0 to 70 °C
power down using charge stored in
-40 to 85 °C
an external 68 μF capacitor. Trans-
-40 to 125 °C
‡ QS 9000 Quality Standard
‡ ESD protection > 2000 V
fers from the EEPROM to the
SRAM (the RECALL operation)
take place automatically on power
(MIL STD 883C M3015.7-HBM) up.
‡ RoHS compliance and Pb- free
Package:SOP 32 (300 mil)
The UL634H256 combines the
high performance and ease of use
of a fast SRAM with nonvolatile
data integrity.
STORE cycles also may be initia-
ted under user control via a soft-
ware sequence or via a single pin
(HSB).
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
Pin Configuration
Pin Description
VCAP
A14
A12
A7
A6
A5
A4
A3
n.c.
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
32
2
31
3
30
4
29
5
28
6
27
7
26
8 _SOP 25
9
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
Top View
VCCX
HSB
W
A13
A8
A9
A11
G
n.c.
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Signal Name
A0 - A14
DQ0 - DQ7
E
G
W
VCCX
VSS
VCAP
HSB
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
Capacitor
Hardware Controlled Store/Busy
August 15, 2006
STK Control #ML0058
1
Rev 1.1