U637H256 Datasheet, PDF (1/14 Pages) List of Unclassifed Manufacturers – CapStore 32K x 8 nvSRAM

Not Recommended For New Designs
U637H256
CapStore 32K x 8 nvSRAM
Features
Description
‡ High-performance CMOS non- The U637H256 has two separate
volatile static RAM 32768 x 8 bits modes of operation: SRAM mode
‡ 25 ns Access Time
and nonvolatile mode. In SRAM
‡ 10 ns Output Enable Access
mode, the memory operates as an
Time
‡ I_CC = 15 mA typ. at 200 ns Cycle
Time
‡ Unlimited Read and Write Cycles
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
to SRAM
mode SRAM functions are disab-
‡ Automatic STORE to EEPROM led.
on Power Down using charge
The U637H256 is a fast static RAM
stored in an integrated capacitor
‡ Software initiated STORE
‡ Automatic STORE Timing
‡ 10⁶ STORE cycles to EEPROM
‡ 100 years data retention in
(25 ns) with a nonvolatile electri-
cally erasable PROM (EEPROM)
element incorporated in each static
memory cell. The SRAM can be
read and written an unlimited num-
EEPROM
ber of times, while independent
‡ Automatic RECALL on Power Up nonvolatile data resides in
‡ Software RECALL Initiation
EEPROM. Data transfers from the
‡ Unlimited RECALL cycles from SRAM to the EEPROM (the
EEPROM
‡ Single 5 V ± 10 % Operation
‡ Operating temperature range:
STORE operation) take place auto-
matically upon power down using
charge stored in an integrated
0 to 70 °C
capacitor. Transfers from the
-40 to 85°C
‡ QS 9000 Quality Standard
EEPROM to the SRAM (the
RECALL operation) take place
(MIL STD 883C M3015.7)
automatically on power up. The
‡ RoHS compliance and Pb- free U637H256 combines the high per-
Package: PDIP28 (600 mil)
formance and ease of use of a fast
SRAM with nonvolatile data inte-
grity.
STORE cycles also may be initia-
ted under user control via a soft-
ware sequence.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
The U637H256 is pin compatible
with standard SRAMs and standard
battery backed SRAMs.
Pin Configuration
Pin Description
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8 ^PDIP 21
9
20
10
19
11
18
12
17
13
16
14
15
VCC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Top View
August 15, 2006
STK Control #ML0056
Signal Name
A0 - A14
DQ0 - DQ7
E
G
W
VCC
VSS
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
1
Rev 1.1