U635H256 Datasheet, PDF (1/14 Pages) Simtek Corporation – PowerStore 32K x 8 nvSRAM

Not Recommended For New Designs
U635H256
PowerStore 32K x 8 nvSRAM
Features
Description
‡ _{High-performance CMOS non}
The U635H256 has two separate
volatile static RAM 32768 x 8 bits modes of operation: SRAM mode
‡ _{25 ns Access Time}
and nonvolatile mode. In SRAM
‡ _{10 ns Output Enable Access}
mode, the memory operates as an
Time
‡ _{ICC = 15 mA typ. at 200 ns Cycle}
Time
‡ _{Automatic STORE to EEPROM}
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
on Power Down using system
mode SRAM functions are disab-
capacitance
‡ _{Software initiated STORE}
‡ _{Automatic STORE Timing}
‡ ₁₀⁶ _{STORE cycles to EEPROM}
‡ _{100 years data retention in}
led.
The U635H256 is a fast static RAM
(25 ns), with a nonvolatile electri-
cally erasable PROM (EEPROM)
element incorporated in each static
EEPROM
memory cell. The SRAM can be
‡ _{Automatic RECALL on Power Up} read and written an unlimited num-
‡ _{Software RECALL Initiation}
ber of times, while independent
‡ _{Unlimited RECALL cycles from} nonvolatile data resides in
EEPROM
‡ _{Single 5 V ± 10 % Operation}
‡ _{Operating temperature range:}
EEPROM. Data transfers from the
SRAM to the EEPROM (the
STORE operation) take place auto-
0 to 70 °C
matically upon power down using
-40 to 85°C
‡ _{QS 9000 Quality Standard}
‡ _{ESD protection > 2000 V}
charge stored in system capaci-
tance. Transfers from the
EEPROM to the SRAM (the
(MIL STD 883C M3015.7-HBM) RECALL operation) take place
‡ _{RoHS compliance and Pb- free} automatically on power up. The
Package: SOP28 (330 mil)
U635H256 combines the high per-
formance and ease of use of a fast
SRAM with nonvolatile data inte-
grity.
STORE cycles also may be initia-
ted under user control via a soft-
ware sequence.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
The U635H256 is pin compatible
with standard SRAMs.
Pin Configuration
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8 ^SOP 21
9
20
10
19
11
18
12
17
13
16
14
15
VCC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Top View
August 15, 2006
STK Control #ML0051
Pin Description
Signal Name
A0 - A14
DQ0 - DQ7
E
G
W
VCC
VSS
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
1
Rev 1.1