U634H256XS Datasheet, PDF (1/17 Pages) Simtek Corporation – PowerStore 32K x 8 nvSRAM Die

Obsolete - Not Recommended for New Designs
U634H256XS
PowerStore 32K x 8 nvSRAM Die
Features
Description
• High-performance CMOS non-
volatile static RAM 32768 x 8 bits
• 25, 35 and 45 ns Access Times
• 10, 15 and 20 ns Output Enable
Access Times
• I_CC = 15 mA typ. at 200 ns Cycle
Time
• Automatic STORE to EEPROM
on Power Down using external
capacitor
• Hardware or Software initiated
STORE
(STORE Cycle Time < 10 ms)
• Automatic STORE Timing
• 10⁵ STORE cycles to EEPROM
• 10 years data retention in
EEPROM
• Automatic RECALL on Power Up
• Software RECALL Initiation
(RECALL Cycle Time < 20 μs)
• Unlimited RECALL cycles from
EEPROM
• Single 5 V ± 10 % Operation
• Operating temperature ranges:
0 to 70 °C
-40 to 85 °C
• QS 9000 Quality Standard
• ESD protection > 2000 V
(MIL STD 883C M3015.7-HBM)
The U634H256XS has two sepa-
rate modes of operation: SRAM
mode and nonvolatile mode. In
SRAM mode, the memory operates
as an ordinary static RAM. In non-
volatile operation, data is transfer-
red in parallel from SRAM to
EEPROM or from EEPROM to
SRAM. In this mode SRAM
functions are disabled.
The U634H256XS is a fast static
RAM (25, 35, 45 ns), with a nonvo-
latile electrically erasable PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation) take place
automatically upon power down
using charge stored in an external
100 μF capacitor.
Transfers from the EEPROM to the
SRAM (the RECALL operation)
take place automatically on power
up.
The U634H256XS combines the
high performance and ease of use
of a fast SRAM with nonvolatile
data integrity.
STORE cycles also may be initia-
ted under user control via a soft-
ware sequence or via a single pad
(HSB).
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
The chips are tested with a
restricted wafer probe program
at room temperature only. Unte-
sted parameters are marked with
a number sign (#).
Pad Configuration
Pad Description
A5
A6 A7 A12 A14 VCAP VCCX HSB W A13 A8
A9
A4
A11
A3
G
A2
A1
A0
A10
E
DQ0 DQ1 DQ2 VSS VCAPDQ3 DQ4 DQ5 DQ6 ^DQ7
Signal Name
A0 - A14
DQ0 - DQ7
E
G
W
VCCX
VSS
VCAP
HSB
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
Capacitor
Hardware Controlled Store/Busy
March 31, 2006
STK Control #ML0049
1
Rev 1.0