SII3114_07 Datasheet, PDF (91/127 Pages) Silicon image – PCI to Serial ATA Controller

Silicon Image, Inc.
SiI3114 PCI to Serial ATA Controller
Data Sheet
Power Management
Power Management in the SiI3114 is controlled by the register bits described in Table 28.
Table 28. Power Management Register Bits
Register
SMisc
SMisc
SError
SMisc
SMisc
SControl
SStatus
Bits
PMCHG
Bit 6
PMMODE
Bits 5,4
W
Bit 18
ComWake
Bit 11
PMREQ
Bits 1,0
IPM
Bits 11-8
IPM
Bits 11-8
Description
This bit reports a change in the Power Management mode. It corresponds to the interrupt
enabled by bit 26 of SIEN.
These bits report the power management mode status: bit 5 corresponds to Slumber mode;
bit 4 to Partial mode. A transition on either of these bits causes a Power Management mode
change interrupt.
ComWake received from the Serial ATA bus
Generates a ComWake condition on the Serial ATA bus
Generates a request from the Host for the Device to go to a Power Management state; bit 1
corresponds to Slumber mode; bit 0 corresponds to Partial mode. These bits are effective
regardless of the state of the HPMDS bit.
This bit field disables transitions to Partial or Slumber power management states; bit 9
corresponds to Slumber mode; bit 8 corresponds to Partial mode.
This bit field reports the power management state; ‘0110’ corresponds to Slumber mode;
‘0010’ corresponds to Partial mode.
Power Management Summary
There are two power management modes: Partial and Slumber. These power management modes may be
software initiated through the SMisc register or device initiated from the Serial ATA device.
Transitions to and from either power management mode generate an interrupt, the Power Management Mode
Change Interrupt, which may be masked in the SMisc register (bit 26).
Partial Power Management Mode
Partial mode may be initiated by software through the SMisc register (bit 0). By setting the bit, the software
causes PMREQ_P primitives (Power Management REQuest – Partial) to be sent to the Serial ATA device, which
will respond with either a PMACK or PMNAK. If a PMACK is received the Partial mode is entered; A PMNAK is
ignored; the request remains asserted.
The Serial ATA device may initiate partial mode. This is indicated by the reception of PMREQ_P primitives from
the device. Software enables the acknowledgement of this request by setting the IPM value in the SControl
register to ‘00x1’ If enabled, a PMACK will be sent to the device; if not enabled, a PMNAK will be sent. When the
request is received and its acknowledgement is enabled, Partial mode is entered.
Partial mode status is reported in both the SStatus register (‘0010’ in the IPM field) and the SMisc register (bit 4).
Partial mode is cleared by setting the ComWake bit in the Smisc register. This will send a COMWAKE signal to
the device through the Serial ATA link to initiate a Partial to On sequence. Partial mode can also be cleared
through receipt of OOB signals from the device.
Slumber Power Management Mode
Slumber mode may be initiated by software through the SMisc register (bit 1). By setting the bit, software causes
PMREQ_S primitives to be sent to the Serial ATA device, which will respond with either a PMACK or PMNAK. If a
PMACK is received the Slumber mode is entered. A PMNAK is ignored; the request remains asserted.
The Serial ATA device may initiate slumber mode. This is indicated by the reception of PMREQ_S primitives.
Software enables the acknowledgement of this request by setting the IPM value in the SControl register to ‘001x’.
© 2007 Silicon Image, Inc.
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SiI-DS-0103-D