SII3124A Datasheet, PDF (68/88 Pages) Silicon image – PCI-X to Serial ATA Controller

PCI-X to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
7.3.1 Port LRAM
Address Offset: 000_H-FFF_H
Access Type: Read/Write
Reset Value: indeterminate
The Port LRAM consists of 31 Slots of 128 bytes each and a 32^nd “Slot” used to hold 16 Port Multiplier Device Specific
Registers.
Address Offset
000_H-07F_H
080_H-0FF_H
100_H-17F_H
180_H-EFF_H
F00_H-F7F_H
F80_H-F83_H
F84_H-F87_H
F88_H-F8B_H
F8C_H-F8F_H
F90_H-FF7_H
FF8_H-FFB_H
FFC_H-FFF_H
Description
Slot 0
Slot 1
Slot 2
Slots 3-29
Slot 30
Port Multiplier Device 0 Status Register
Port Multiplier Device 0 QActive Register
Port Multiplier Device 1 Status Register
Port Multiplier Device 1 QActive Register
Port Multiplier Device Registers for Devices 2-14
Port Multiplier Device 15 Status Register
Port Multiplier Device 15 QActive Register
Table 7-5 Port LRAM layout
Address Offset
000_H-01F_H
020_H-02F_H
030_H-03F_H
040_H-047_H
040_H-07F_H
1C00_H-1C07_H
Description
Current FIS and Control
Scatter/Gather Entry 0 or ATAPI command packet
Scatter/Gather Entry 1
Command Activation Register (Actual)
Scatter/Gather Table
Command Activation Register (Shadow)
Port Request
Block (PRB)
Table 7-6 Port LRAM Slot layout
A Port LRAM Slot is 128 bytes used to define Serial-ATA commands. The addresses shown above are for slot 0.
7.3.2 Port Slot Status
Address Offset: 1800_H
Access Type: Read
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Slot Status
This register provides the status for the 31 Command Slots for the Serial-ATA port. This register also appears along with the
Port Status register of the other 3 ports in Global register space. Reading this register will clear the Command Completion
Status for the port if the Interrupt No Clear on Read bit (bit 3) of the Port Control register is 0. The register bits are defined
below.
• Bit [31]: Attention (R) – This bit indicates that something occurred in the port that requires the attention of the host.
Other port registers must be examined to determine the origin of the error. This bit is the logical OR of the masked
interrupt conditions reported in the Port Interrupt Status register.
• Bit [30:0]: Slot Status (R) – These bits are the Active status bits corresponding to Slot numbers 30 to 0. The Active
status bit is set when a command is transferred to the Slot RAM.
© 2006 Silicon Image, Inc.
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SiI-DS-0160-C