SII1161 Datasheet, PDF (40/46 Pages) Silicon image – PanelLink Receiver

VCCPIN
C1
C2
L1
C3
SiI 1161 PanelLink Receiver
Data Sheet
VCC
Figure 26. Decoupling and Bypass Schematic
The values shown in Table 20 are recommendations for noise suppression in the 1-2MHz range that should be
adjusted according to the noise characteristics of the specific board-level design. Pins in one group (such as
OVCC) may share L1 and C3, each pin having C1 and C2 placed as close to the pin as possible. This filter circuit
should be placed on planes where power supply ripple could exceed the VCC noise specification.
Table 20. Recommended Components for 1-2MHz Noise Suppression
C1
C2
C3
L1
100 – 300 pF
0.1 µF
10 µF
Ferrite, 200+ Ω
@ 100MHz
The PLL circuit that is powered from PVCC is more sensitive to noise in the 100-200kHz range. If the power
supply is prone to generation of noise in this range in excess of the PV_CCN specification, the component values
shown in Table 21 should be used on the PVCC plane.
Table 21. Recommended Components for 100-200kHz Noise Suppression on PVCC
C1
C2
C3
L1
not used
6.8 µF
10 µF
10 µH inductor
Series Damping Resistors on Outputs
Small (~22 ohms) series resistors are effective in lowering the data-related emissions and reducing reflections.
Series resistors should be placed close to the output pins on the receiver chip, as shown in Figure 27.
RX
Figure 27. Receiver Output Series Damping Resistors
SiI-DS-0096-D
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