SII164 Datasheet, PDF (17/33 Pages) Silicon image – Transmitter uses PanelLink Digital technology

SiI 164 PanelLink Transmitter
Data Sheet
I²C Register Definitions (cont’d)
Register Name
CFG[7:0]
PFEN
PLLF[3:1]
SCNT
DK[3:1]
DKEN
Access
RO
RW
RW
RW
RW
RW
Description
Contains state of inputs D[23:16]. These pins can be used to provide user selectable
configuration data through the I²C bus. Only available in 12-bit mode
PLL Filter Enable in the VDJK Register.
1 – To enable PLL Filter (recommended setting)
0 – To disable PLL Filter
Set characteristics of PLL filter in the VDJK register
100 – Recommended value
SYNC Continuous
1 – To enable (recommended setting)
0 – To disable
De-skewing Setting. Increment 260psec.
000 – 1 step -> minimum setup / maximum hold
001 – 2 step
010 – 3 step
011 – 4 step
100 – 5 step -> default (recommended setting)
101 – 6 step
110 – 7 step
111 – 8 step -> maximum setup / minimum hold
Please see Data De-Skew Feature for an illustration
De-skewing Enable through DK[3:1] bits. When DKEN pin is HIGH via pin or set to 1,
then De-skew is enabled. When set to 0 De-skew is disabled. Please see Data De-
skew Feature for an illustration.
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SiI-DS-0021-C