SI3225-FQ Datasheet, PDF (17/108 Pages) Silicon image – DUAL PROSLIC® PROGRAMMABLE CMOS SLIC/CODEC

Si3220/Si3225
Table 13. Switching Characteristics—PCM Highway Interface
(V_DD, V_DD1–V_DD4 = 3.13 to 5.25 V, T_A = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade, C_L = 20 pF)
Parameter
Symbol
Test
Conditions
Min¹
Typ¹
Max^{1 Units}
PCLK Period
t_p
122
—
3906
Valid PCLK Inputs
—
256
—
—
512
—
—
768
—
—
1.024
—
—
1.536
—
—
1.544
—
—
2.048
—
—
4.096
—
—
8.192
—
FSYNC Period²
t_fs
—
125
—
PCLK Duty Cycle Tolerance
t_dty
40
50
60
PCLK Period Jitter Tolerance
t_jitter
—
—
±120
Rise Time, PCLK
t_r
—
—
25
Fall Time, PCLK
t_f
—
—
25
Delay Time, PCLK Rise to DTX Active
t_d1
—
—
20
Delay Time, PCLK Rise to DTX
t_d2
Transition
—
—
20
Delay Time, PCLK Rise to DTX
t_d3
Tristate³
—
—
20
Setup Time, FSYNC to PCLK Fall
t_su1
25
—
—
Hold Time, FSYNC to PCLK Fall
t_h1
20
—
—
Setup Time, DRX to PCLK Fall
t_su2
25
—
—
Hold Time, DRX to PCLK Fall
t_h2
20
—
—
FSYNC Pulse Width
t_wfs
t_p/2
—
125 µs–t_p
Notes:
1. All timing is referenced to the 50% level of the waveform. Input test levels are V_{IH –} V_{I/O –}0.4 V, V_IL = 0.4 V.
2. FSYNC source is assumed to be 8 kHz under all operating conditions.
3. Spec applies to PCLK fall to DTX tristate when that mode is selected.
ns
kHz
kHz
kHz
MHz
MHz
MHz
MHz
MHz
MHz
µs
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. 1.0
17