EM351_12 Datasheet, PDF (101/245 Pages) Silicon Laboratories – High-Performance, Integrated ZigBee/802.15.4 System-on-Chip

EM351 / EM357
Figure 8-3. UART Character Frame Format
UART Character Frame Format
(optional sections are in italics)
TXD
or
RXD
Idle time
Start
Bit
Data
Bit 0
Data
Bit 1
Data
Bit 2
Data
Bit 3
Data
Bit 4
Data
Bit 5
Data
Bit 6
Data
Bit 7
Parity Stop Stop
Bit
Bit Bit
Next
Start Bit
or
IdleTime
8.6.3 FIFOs
Characters transmitted and received by the UART are buffered in the transmit and receive FIFOs that are both
4 entries deep (see Figure 8-4). When software writes a character to the SC1_DATA register, it is pushed onto
the transmit FIFO. Similarly, when software reads from the SC1_DATA register, the character returned is
pulled from the receive FIFO. If the transmit and receive DMA channels are used, the DMA channels also write
to and read from the transmit and receive FIFOs.
Figure 8-4. UART FIFOs
RXD
Receive Shift Register
Parity/Frame Errors
Transmit Shift Register
TXD
SC1_DATA (read)
SC1_UARTSTAT
SC1_DATA (write)
CPU and DMA
Channel Access
8.6.4 RTS/CTS Flow control
RTS/CTS flow control, also called hardware flow control, uses two signals (nRTS and nCTS) in addition to
received and transmitted data (see Figure 8-5). Flow control is used by a data receiver to prevent buffer
overflow, by signaling an external device when it is and is not allowed to transmit.
Figure 8-5. RTS/CTS Flow Control Connections
EM350
UART Receiver
RXD
nRTS
TXD
nCTS
Other Device
UART Transmitter
UART Transmitter
TXD
nCTS
RXD
nRTS
UART Receiver
The UART RTS/CTS flow control options are selected by the SC_UARTFLOW and SC_UARTAUTO bits in the
SC1_UARTCFG register (see Table 8-12). Whenever the SC_UARTFLOW bit is set, the UART will not start
transmitting a character unless nCTS is low (asserted). If nCTS transitions to the high state (deasserts) while a
character is being transmitted, transmission of that character continues until it is complete.
8-27
Final
120-035X-000M