550AD30M7200DG Datasheet, PDF (1/15 Pages) Silicon image – VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO) 10 MHZ TO 1.4 GHZ

Si550
REVISION D
VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO)
10 MHZ TO 1.4 GHZ
Features
 Available with any frequency from  Internal fixed crystal frequency
10 to 945 MHz and select
ensures high reliability and low
frequencies to 1.4 GHz
aging
 3rd generation DSPLL^® with
 Available CMOS, LVPECL,
superior jitter performance (0.5 ps) ^{LVDS, and CML outputs}
 3x better temperature stability than ^{ 3.3, 2.5, and 1.8 V supply options}
SAW-based oscillators
 Industry-standard 5 x 7 mm
 Excellent PSRR performance
package and pinout
 Pb-free/RoHS-compliant
Applications
 SONET/SDH
 xDSL
 10 GbE LAN/WAN
 Low-jitter clock generation
 Optical modules
 Clock and data recovery
Description
The Si550 VCXO utilizes Silicon Laboratories’ advanced DSPLL^® circuitry to
provide a low-jitter clock at high frequencies. The Si550 supports any
frequency from 10 to 945 MHz and select frequencies to 1417 MHz. Unlike
traditional VCXOs, where a different crystal is required for each output
frequency, the Si550 uses one fixed crystal to provide a wide range of output
frequencies. This IC-based approach allows the crystal resonator to provide
exceptional frequency stability and reliability. In addition, DSPLL clock
synthesis provides superior supply noise rejection, simplifying the task of
generating low-jitter clocks in noisy environments typically found in
communication systems. The Si550 IC-based VCXO is factory-configurable
for a wide variety of user specifications, including frequency, supply voltage,
output format, tuning slope, and temperature stability. Specific configurations
are factory programmed at time of shipment, thereby eliminating the long
lead times associated with custom oscillators.
Functional Block Diagram
VDD
Si5602
Ordering Information:
See page 10.
Pin Assignments:
See page 9.
(Top View)
VC 1
OE 2
GND 3
6
VDD
5 CLK–
4 CLK+
Fixed
Frequency
XO
Any-Frequency
10 MHz–1.4 GHz
DSPLL^®
Clock Synthesis
CLK+
CLK–
Vc
ADC
OE
Rev. 1.1 4/13
GND
Copyright © 2013 by Silicon Laboratories
Si550