SD4870TR Datasheet, PDF (5/8 Pages) Silan Microelectronics Joint-stock – CURRENT MODE PWM CONTROLLER

Light Load Mode
In no load or light load condition, major power loss of total power consumption is from switching loss on the
MOSFET transistor switching loss, the core loss of the transformer loss and the loss on the external snubber
circuit loss become the majority in total power loss. The value of those power loss is proportional to switching
actions within a fixed period of time. So reducing number of switching actions leads to reduction of power loss.
SD4870 enters Light Load Mode in no load or light load condition. The gate drive output switches only when
output DC voltage drops below a present level and the switching frequency reduces. Otherwise the gate drive
remains at off state.
Oscillation Frequency Setting
The oscillation frequency is determined by resistor connected between RI and GND. The relationship between
the value of this resistor and frequency are shown below
f_S
=
6500
R_RI
(kHz) ^,
where
RRI
is
the
value
of
external
resistor
and
its
unit
is
KΩ.
Current Sense and LEB
At switching leading edge time, the current spike due to Snubber diode reverse recovery should be chopped off.
And this is available through internal LEB (Leading Edge Blanking) circuit. So that the external RC filter circuit on
SENSE input is no longer required.
During the blanking period, the PWM comparator and OC comparator are disabled and MOSFET transistor
keeps turn-on state if MOSFET turns on. The minimum on time of MOSFET is LEB time.
Gate Drive
GATE pin is connected to external MOSFET’s gate for switch control. Too weak the gate drive ability results in
more switch loss of MOSFET while too strong gate drive compromises the EMI performance.
A good tradeoff is achieved through the totem pole gate drive design with appropriate output ability and dead
time control.
Protection controls
SD4870 offers complete protection functions including cycle-by-cycle over current protection, over load protection,
VDD input voltage over voltage and under voltage protection, etc.
Constant output power limit over universal input voltage range is achived with over current protection threshold
line voltage compensation to over current protection threshold.
VDD is supplies by transformer auxiliary winding output. It is clamped when VDD is higher than clamp threshold
value. The MOSFET is shut down when VDD drops below UVLO threshold voltage and IC enters power on
startup sequence thereafter.
When FB input voltage is higher than over load threshold voltage for more than TD_OL, the MOSFET is shut
down and VDD voltage drops. IC restarts when VDD is lower than UVLO threshold voltage.
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http://www.silan.com.cn
REV:1.0 2009.09.22
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