EM341 Datasheet, PDF (91/237 Pages) Silicon Laboratories – High-Performance, Integrated RF4CE System-on-Chip

EM341
8.6.2. Set Up and Configuration
The UART baud rate clock is produced by a programmable baud generator starting from the 24 Hz clock:
baud = ²--₂--⁴-_N----^M--+---^H--_F--^z--
The integer portion of the divisor, N, is written to the SC1_UARTPER register and the fractional part, F, to the
SC1_UARTFRAC register. Table 8.11 shows the values used to generate some common baud rates and their
associated clock frequency error. The UART requires an internal clock that is at least eight times the baud rate
clock, so the minimum allowable setting for SC1_UARTPER is 8.
Table 8.11. UART Baud Rate Divisors for Common Baud Rates
Baud Rate
(bits/sec)
300
2400
4800
9600
19200
38400
57600
115200
230400
460800
921600
SC1_UARTPER
40000
5000
2500
1250
625
312
208
104
52
26
13
SC1_UARTFRAC
0
0
0
0
0
1
1
0
0
0
0
Baud Rate Error (%)
0
0
0
0
0
0
– 0.08
+ 0.16
+ 0.16
+ 0.16
+ 0.16
The UART can miss bytes when the inter-byte gap is long or there is a baud rate mismatch between receiver and
transmitter. The UART may detect a parity and/or framing error on the corrupted byte, but there will not necessarily
be any error detected.
The UART is best operated in systems where the other side of the communication link also uses a crystal as its
timing reference, and baud rates should be selected to minimize the baud rate mismatch to the crystal tolerance.
Additionally, UART protocols should contain some form of error checking (for example CRC) at the packet level to
detect, and retry in the event of errors. Since the probability of corruption is low, there would only be a small effect
on UART throughput due to retries.
Errors may occur when:
T_gap  _b----_a----_u----_d---¹-_--⁰---_F-⁶---_e----_r--_r---_o---_r-
Where:
T_gap= inter-byte gap in seconds
baud = baud rate in bps
Ferror = relative frequency error in ppm
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Rev 1.0