SI4704 Datasheet, PDF (9/36 Pages) Silicon Laboratories – Worldwide FM band support (64-108 MHz) integrated antenna support EN55020 compliant

Table 6. 3-Wire Control Interface Characteristics
(V_DD = 2.7 to 5.5 V, V_IO = 1.85 to 3.6 V, T_A = –20 to 85 °C)
Parameter
Symbol
Test Condition
SCLK Frequency
SCLK High Time
SCLK Low Time
SDIO Input, SEN to SCLK Setup
SDIO Input to SCLK Hold
SEN Input to SCLK Hold
SCLK to SDIO Output Valid
SCLK to SDIO Output High Z
SCLK, SEN, SDIO, Rise/Fall Time
f_CLK
t_HIGH
t_LOW
t_S
t_HSDIO
t_HSEN
t_CDV
t_CDZ
t_R, t_F
Read
Read
Si4704/05-C40
Min
Typ
Max Unit
0
—
2.5
MHz
25
—
—
ns
25
—
—
ns
20
—
—
ns
10
—
—
ns
10
—
—
ns
2
—
25
ns
2
—
25
ns
—
—
10
ns
SCLK 70%
30%
SEN ^70%
30%
tR
tF
tS
tHSDIO
tHIGH tLOW
tS
tHSEN
SDIO 70%
30%
A6-A5,
A7
R/W,
A0
A4-A1
D15
D14-D1
D0
Address In
Data In
Figure 4. 3-Wire Control Interface Write Timing Parameters
SCLK 70%
30%
tS
SEN 70%
30%
tHSDIO
tS
tCDV
tHSEN
tCDZ
70%
SDIO
30%
A6-A5,
A7
R/W,
A0
A4-A1
D15
D14-D1
D0
Address In
½ Cycle Bus
Turnaround
Data Out
Figure 5. 3-Wire Control Interface Read Timing Parameters
Rev. 1.0
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