ISL6455 Datasheet, PDF (9/13 Pages) Intersil Corporation – Low shutdown supply current

ISL6455, ISL6455A
Functional Description
The ISL6455 is a 3-in-1 multi-output regulator designed for
FPGA and wireless chipset power applications. The device
integrates a single synchronous buck regulator with dual
LDOs. The PWM output can be set by choosing appropriate
values for Re and Rf. At a setting of 1.8V the synchronous
buck regulator provides for an efficiency greater than 92%.
The LDO1 can be set with resistor pair Rc and Rd. The
LDO2 can be set with the resistor pair Ra and Rb.
Undervoltage lock-out (UVLO) prevents the converter from
turning on when the input voltage is less than 2.6V typical.
Additional blocks include output overcurrent protection,
thermal sensor, PGOOD detectors, RESET function and
shutdown logic.
Synchronous Buck Regulator
The synchronous buck regulator with integrated N-Channel
and P-Channel power MOSFETs and external voltage
setting resistors provides for adjustable voltages from the
PWM. Synchronous rectification with internal MOSFETs is
used to achieve higher efficiency and reduced number of
external components. Operating frequency is typically
750kHz allowing the use of smaller inductor and capacitor
values. The device can be synchronized to an external clock
signal in the range of 500kHz to 1MHz. The PG_PWM
output indicates loss of regulation on PWM output.
The PWM architecture uses a peak current mode control
scheme with internal slope compensation. At the beginning
of each clock cycle, the high side P-channel MOSFET is
turned on. The current in the inductor ramps up and is
sensed via an internal circuit. The error amplifier sets the
threshold for the PWM comparator. The high side switch is
turned off when the sensed inductor current reaches this
threshold. After a minimum dead time preventing shoot
through current, the low side N-Channel MOSFET will be
turned on, and the current ramps down again. As the clock
cycle is completed, the low side switch will be turned off and
the next clock cycle starts.
The control loop is internally compensated reducing the
amount of external components.
The switch current is internally sensed and the maximum
peak current limit is 1300mA.
Synchronization
The typical operating frequency for the converter is 750kHz
if no clock signal is applied to SYNC pin. It is possible to
synchronize the converter to an external clock within a
frequency range from 500kHz to 1MHz. The device
automatically detects the rising edge of the first clock and
will synchronize immediately to the external clock. If the
clock signal is stopped, the converter automatically switches
back to the internal clock and continues operation without
interruption. The switch-over will be initiated if no rising edge
on the SYNC pin is detected for a duration of two internal
1.3µs clock cycles.
Soft-Start
As the EN (Enable) pin goes high, the soft-start function will
generate an internal voltage ramp. This causes the start-up
current to slowly rise preventing output voltage overshoot
and high in-rush currents. The soft-start duration is typically
5.5ms with 750kHz switching frequency. When the soft-start
is completed, the error amplifier will be connected directly to
the internal voltage reference. The SYNC input is ignored
during soft-start.
Enable PWM
Logic low on EN pin forces the PWM section into shutdown.
In shutdown all the major blocks of the PWM including power
switches, drivers, voltage reference, and oscillator are
turned off.
Power Good (PG_PWM)
When chip is enabled, this output is asserted HIGH, when
V_OUT is within 8% of V_OPWM value and active low outside
this range. When the PWM is disabled, the output is active
low.
Leave the PG_PWM pin unconnected when not used.
PWM Overvoltage and Overcurrent Protection
The PWM output current is sampled at the end of each PWM
cycle. Should it exceed the overcurrent limit, a 4-bit up/down
counter counts up two LSB. Should it not be in overcurrent,
the counter counts down one LSB, (but the counter will not
"rollover" or count below 0000). If > 33% of the PWM cycles
go into overcurrent, the counter rapidly reaches count 1111
and the PWM output is shut down and the soft-start counter
is reset. After 16 clocks the PWM, output is enabled and the
SS cycle is started.
If V_OUT exceeds the overvoltage limit for 32 consecutive
clock cycles, the PWM output is shut off and the SS counters
reset. The chip waits for the output voltage to go below
undervoltage (8% below nominal) then goes through two
dummy soft-start cycles (PWM disabled for 2 SS cycles =
11ms) and then starts a normal soft-start cycle.
PG_LDO
PG_LDO is an open drain pulldown NMOS output that will
sink 1mA at 0.4V maximum. It goes to the active low state if
either LDO output is out of regulation by a value greater than
15%. When the LDO is disabled, the output is active low.
LDO Regulators
Each LDO consists of a 1.184V reference, error amplifier,
MOSFET driver, P-Channel pass transistor, and dual-mode
comparator. The voltage is set by means of two resistors: the
Ra and Rb for LDO2 and Rc and Rd for LDO1. The 1.184V
band gap reference is connected to the error amplifier’s
inverting input. The error amplifier compares this reference
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FN9196.1
February 19, 2014