CP2400 Datasheet, PDF (89/110 Pages) Silicon Laboratories – 128/64 SEGMENT LCD DRIVER

CP2400/1/2/3
SFR Definition 12.7. LCD0PWR: LCD0 Power Register
Bit
7
6
5
4
3
2
1
0
Name
CPCLK[1:0]
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Address = 0x9B
Bit
Name
Function
7:5 Reserved Read = 000b. Must Write 000b.
4:3 CPCLK[1:0] Charge Pump Clock Select.
00: 1 MHz charge pump clock (normal operation).
01: 2 MHz charge pump clock.
10: 0.5 MHz charge pump clock.
11: 0.67 MHz charge pump clock.
2:0 Reserved Read = 000b. Must Write 000b.
Rev. 1.0
89