SI4730-D60-GU Datasheet, PDF (8/42 Pages) Silicon Laboratories – BROADCAST AM/FM/SW/LW RADIO RECEIVER

Si4730/31/34/35-D60
Table 4. 2-Wire Control Interface Characteristics^1,2,3
(V_A = 2.7 to 5.5 V, V_D = 1.62 to 3.6 V, T_A = –20 to 85 °C)
Parameter
SCLK Frequency
SCLK Low Time
SCLK High Time
SCLK Input to SDIO  Setup
(START)
SCLK Input to SDIO  Hold
(START)
SDIO Input to SCLK  Setup
SDIO Input to SCLK  Hold^4,5
SCLK input to SDIO  Setup
(STOP)
STOP to START Time
SDIO Output Fall Time
Symbol Test Condition
Min
Typ
f_SCL
t_LOW
t_HIGH
t_SU:STA
0
—
1.3
—
0.6
—
0.6
—
t_HD:STA
0.6
—
t_SU:DAT
t_HD:DAT
t_SU:STO
100
—
0
—
0.6
—
t_BUF
t_f:OUT
1.3
—
—
20 + 0.11--^C--_p---^b-_F--
Max
Unit
400
kHz
—
µs
—
µs
—
µs
—
µs
—
ns
900
ns
—
µs
—
µs
250
ns
SDIO Input, SCLK Rise/Fall Time
t_f:IN
t_r:IN
—
20 + 0.11--^C--_p---^b-_F--
300
ns
SCLK, SDIO Capacitive Loading
C_b
—
—
50
pF
Input Filter Pulse Suppression
t_SP
—
—
50
ns
Notes:
1. When V_D = 0 V, SCLK and SDIO are low impedance.
2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high
until after the first start condition.
4. The Si473x-D60 delays SDIO by a minimum of 300 ns from the V_IH threshold of SCLK to comply with the minimum
t_HD:DAT specification.
5. The maximum t_HD:DAT has only to be met when f_SCL = 400 kHz. At frequencies below 400 KHz, t_HD:DAT may be
violated as long as all other timing parameters are met.
8
Rev. 1.2