EZR32HG220 Datasheet, PDF (8/86 Pages) Silicon Laboratories – Consumer electronics

EZR32HG220 Data Sheet
System Overview
3.2 Configuration Summary
The features of the EZR32HG220 are a subset of the feature set described in the EZR32HG Reference Manual. The table below de-
scribes device specific implementation of the features.
Table 3.2. Configuration Summary
Module
Cortex-M0+
DBG
MSC
DMA
RMU
EMU
CMU
WDOG
PRS
I2C0
UART0
LEUART0
USARTRF1
TIMER0
TIMER1
TIMER2
RTC
PCNT0
VCMP
ADC0
IDAC0
AES
GPIO
Configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration with IrDA and I2S
Full configuration
Reduced configuration
Full configuration with DTI
Full configuration
Full configuration
Full configuration
Full configuration, 16-bit count register
Full configuration
Full configuration
Full configuration
Full configuration
27 pins
Pin Connections
NA
DBG_SWCLK, DBG_SWDIO
NA
NA
NA
NA
CMU_CLK0, CMU_CLK1
NA
NA
I2C0_SDA, I2C0_SCL
US0_TX, US0_RX, US0_CLK, US0_CS
LEU0_TX, LEU0_RX
USRF1_RX, USRF1_TX
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIM1_CC[2:0]
TIM2_CC[2:0]
NA
PCNT0_S[1:0]
NA
ADC0_CH[7, 6, 5, 4, 1, 0]
IDAC0_OUT
NA
Available pins are shown in 5.4 GPIO Pin-
out Overview
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