EFM32WG842 Datasheet, PDF (75/78 Pages) Silicon Laboratories – Operation from backup battery when main power drains out

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List of Figures
2.1. Block Diagram ....................................................................................................................................... 3
2.2. EFM32WG842 Memory Map with largest RAM and Flash sizes ....................................................................... 9
3.1. EM1 Current consumption with all peripheral clocks disabled and HFXO running at 48MHz ................................. 13
3.2. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 28MHz ............................... 13
3.3. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 21MHz ............................... 14
3.4. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 14MHz ............................... 14
3.5. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 11MHz ............................... 15
3.6. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 6.6MHz .............................. 15
3.7. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 1.2MHz .............................. 16
3.8. EM2 current consumption. RTC prescaled to 1kHz, 32.768 kHz LFRCO. ......................................................... 16
3.9. EM3 current consumption. ..................................................................................................................... 17
3.10. EM4 current consumption. ................................................................................................................... 17
3.11. Typical Low-Level Output Current, 2V Supply Voltage ................................................................................ 21
3.12. Typical High-Level Output Current, 2V Supply Voltage ................................................................................ 22
3.13. Typical Low-Level Output Current, 3V Supply Voltage ................................................................................ 23
3.14. Typical High-Level Output Current, 3V Supply Voltage ................................................................................ 24
3.15. Typical Low-Level Output Current, 3.8V Supply Voltage .............................................................................. 25
3.16. Typical High-Level Output Current, 3.8V Supply Voltage ............................................................................. 26
3.17. Calibrated LFRCO Frequency vs Temperature and Supply Voltage .............................................................. 28
3.18. Calibrated HFRCO 1 MHz Band Frequency vs Supply Voltage and Temperature ............................................ 29
3.19. Calibrated HFRCO 7 MHz Band Frequency vs Supply Voltage and Temperature ............................................ 30
3.20. Calibrated HFRCO 11 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 30
3.21. Calibrated HFRCO 14 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 30
3.22. Calibrated HFRCO 21 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 31
3.23. Calibrated HFRCO 28 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 31
3.24. Integral Non-Linearity (INL) ................................................................................................................... 37
3.25. Differential Non-Linearity (DNL) .............................................................................................................. 37
3.26. ADC Frequency Spectrum, Vdd = 3V, Temp = 25°C ................................................................................. 38
3.27. ADC Integral Linearity Error vs Code, Vdd = 3V, Temp = 25°C ................................................................... 39
3.28. ADC Differential Linearity Error vs Code, Vdd = 3V, Temp = 25°C ............................................................... 40
3.29. ADC Absolute Offset, Common Mode = Vdd /2 ........................................................................................ 41
3.30. ADC Dynamic Performance vs Temperature for all ADC References, Vdd = 3V .............................................. 41
3.31. ADC Temperature sensor readout ......................................................................................................... 42
3.32. OPAMP Common Mode Rejection Ratio ................................................................................................. 45
3.33. OPAMP Positive Power Supply Rejection Ratio ........................................................................................ 45
3.34. OPAMP Negative Power Supply Rejection Ratio ...................................................................................... 46
3.35. OPAMP Voltage Noise Spectral Density (Unity Gain) V_out=1V ..................................................................... 46
3.36. OPAMP Voltage Noise Spectral Density (Non-Unity Gain) .......................................................................... 46
3.37. ACMP Characteristics, Vdd = 3V, Temp = 25°C, FULLBIAS = 0, HALFBIAS = 1 ............................................. 48
3.38. SPI Master Timing ............................................................................................................................... 52
3.39. SPI Slave Timing ................................................................................................................................ 53
4.1. EFM32WG842 Pinout (top view, not to scale) ............................................................................................. 55
4.2. Opamp Pinout ...................................................................................................................................... 63
4.3. TQFP64 .............................................................................................................................................. 64
5.1. TQFP64 PCB Land Pattern ..................................................................................................................... 66
5.2. TQFP64 PCB Solder Mask ..................................................................................................................... 67
5.3. TQFP64 PCB Stencil Design ................................................................................................................... 68
6.1. Example Chip Marking (top view) ............................................................................................................. 69
2014-06-13 - EFM32WG842FXX - d0196_Rev1.40
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