ISL1904 Datasheet, PDF (7/21 Pages) Intersil Corporation – Dimmable AC Mains LED Driver with PFC and Primary Side Regulation

Pin Configuration
ISL1904
ISL1904
(16 LD QSOP)
TOP VIEW
1 VDD
OUT 16
2 OFFREF PWMOUT 15
3 VREF
DHC 14
4 IOUT
GND 13
5 CS+
AC 12
6 OC
OVP 11
7 FB
RAMP 10
8 DELADJ
VERR 9
Pin Descriptions
PIN # SYMBOL
DESCRIPTION
1
VDD VDD is the power connection for the IC. To optimize noise immunity, bypass VDD to GND with a ceramic capacitor as close to the
VDD and GND pins as possible.
2 OFFREF Sets the reference level to disable the driver at light loading. The turn-off reference can be set at any level between 0 and 0.6V,
corresponding to 0 to 100% of output loading. This feature is normally used in triac-based wall dimmer applications to disable the
output before the dimmer becomes unstable due to insufficient holding current.
3
VREF The 5.40V reference voltage output having ±100 mV tolerance over line, load and operating temperature. Bypass to GND with a
0.1µF to 3.3µF low ESR capacitor.
4
IOUT A PWM voltage signal with amplitude and duty cycle proportional to the peak switching current used to determine the output
current.
5
CS+ The input for the CrCM current sense circuit. This input monitors the winding current to determine the critical conduction operating
point.
6
OC The input to the load current sensing circuitry and the peak overcurrent comparator. The signal is sampled at the peak current level
for each switching cycle, amplified, and output on IOUT as a PWM signal. It must be scaled, filtered and averaged prior to being
applied to the FB pin of the EA. The overcurrent comparator threshold is set at 600mV nominal. Peak OCP performs cycle-by-cycle
over current protection. OCP includes leading-edge-blanking (LEB), which blocks the signal at the beginning of the OUT pulse for the
duration of the blanking period and when the OUT pulse is low.
7
FB FB is the inverting input to the error amplifier (EA). The feedback signal from IOUT, after being scaled and filtered, is applied to the
error amplifier.
8 DELADJ Sets delay before a new switching cycles starts. This adjustment allows the user to delay the next switching cycle until the switching
FET drain-source voltage reaches a minimum value to allow quasi-ZVS (Zero Voltage Switching) operation. A resistor to ground
programs the delay. Pulling DELADJ to VREF disables the CrCM oscillator.
9
VERR Output of the error amplifiers and the control voltage input to the inverting input of the PWM comparator. VERR cannot source
current and requires an external pull-up resistor to VREF.
10 RAMP This is the input for the sawtooth waveform for the PWM comparator. Using an RC from VREF, a sawtooth waveform is created for
use by the PWM. It is compared to the error amplifier output, Verr, to create the PWM control signal. The RAMP pin is shorted to
GND at the termination of the PWM signal.
11
OVP Input to detect an overvoltage (OV) condition on the output. Since the control variable is output current, a fault that results in an
open circuit will cause excessive output voltage. The circuit hysteresis is a switched current source that is active when the OV
threshold is exceeded.
12
AC Input to sense AC voltage presence and amplitude. A resistor divider from line and neutral/line and circuit ground is used to detect
the AC voltage.
13
GND Signal and power ground connections for this device. Due to high peak currents and high frequency operation, a low impedance
layout is necessary. Ground planes and short traces are highly recommended.
14
DHC An open drain FET used to load the input voltage to pre-load a triac-based dimmer so that adequate holding current is maintained.
7
FN8286.1
September 20, 2012