EFM32LG390 Datasheet, PDF (67/82 Pages) Silicon Laboratories – Output state retention and wake-up from Shutoff Mode

Alternate
Functionality
0
1
US2_CLK
PC4
PB5
US2_CS
PC5
PB6
US2_RX
PC3
PB4
US2_TX
PC2
PB3
USB_DM
USB_DMPU
USB_DP
USB_ID
USB_VBUS
USB_VBUSEN
USB_VREGI
USB_VREGO
PF10
PD2
PF11
PF12
USB_VBUS
PF5
USB_VREGI
USB_VREGO
...the world's most energy friendly microcontrollers
LOCATION
2
3
4
5
6
Description
USART1 Synchronous mode Master Output / Slave Input
(MOSI).
USART2 clock input / output.
USART2 chip select input / output.
USART2 Asynchronous Receive.
USART2 Synchronous mode Master Input / Slave Output
(MISO).
USART2 Asynchronous Transmit.Also used as receive in-
put in half duplex communication.
USART2 Synchronous mode Master Output / Slave Input
(MOSI).
USB D- pin.
USB D- Pullup control.
USB D+ pin.
USB ID pin. Used in OTG mode.
USB 5 V VBUS input.
USB 5 V VBUS enable.
USB Input to internal 3.3 V regulator
USB Decoupling for internal 3.3 V USB regulator and reg-
ulator output
4.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32LG390 is shown in Table 4.3 (p. 67) . Each GPIO port is
organized as 16-bit ports indicated by letters A through F, and the individual pin on this port in indicated
by a number from 15 down to 0.
Table 4.3. GPIO Pinout
Port
Port A
Port B
Port C
Port D
Port E
Port F
Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
-
-
-
- PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0
-
-
-
PF12 PF11 PF10 PF9 PF8 PF7 PF6 PF5
-
-
PF2 PF1 PF0
4.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32LG390 is shown in Figure 4.2 (p. 68) .
2014-06-13 - EFM32LG390FXX - d0113_Rev1.30
67
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