EFM32HG309 Datasheet, PDF (6/69 Pages) Silicon Laboratories – Output state retention and wake-up from Shutoff Mode

Preliminary
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2.1.20 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits
at up to one million samples per second. The integrated input mux can select inputs from 2 external
pins and 6 internal signals.
2.1.21 Current Digital to Analog Converter (IDAC)
The current digital to analog converter can source or sink a configurable constant current, which can
be output on, or sinked from pin or ADC. The current is configurable with several ranges of various
step sizes.
2.1.22 Advanced Encryption Standard Accelerator (AES)
The AES accelerator performs AES encryption and decryption with 128-bit. Encrypting or decrypting one
128-bit data block takes 52 HFCORECLK cycles with 128-bit keys. The AES module is an AHB slave
which enables efficient access to the data and key registers. All write accesses to the AES module must
be 32-bit operations, i.e. 8- or 16-bit operations are not supported.
2.1.23 General Purpose Input/Output (GPIO)
In the EFM32HG309, there are 24 General Purpose Input/Output (GPIO) pins, which are divided into
ports with up to 16 pins each. These pins can individually be configured as either an output or input. More
advanced configurations like open-drain, filtering and drive strength can also be configured individually
for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Timer PWM
outputs or USART communication, which can be routed to several locations on the device. The GPIO
supports up to 10 asynchronous external pin interrupts, which enables interrupts from any pin on the
device. Also, the input value of a pin can be routed through the Peripheral Reflex System to other
peripherals.
2.2 Configuration Summary
The features of the EFM32HG309 is a subset of the feature set described in the EFM32HG Reference
Manual. Table 2.1 (p. 6) describes device specific implementation of the features.
Table 2.1. Configuration Summary
Module
Cortex-M0+
DBG
MSC
DMA
RMU
EMU
CMU
WDOG
PRS
USB
I2C0
USART0
USART1
Configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration with IrDA and I2S
Full configuration with I2S and IrDA
Pin Connections
NA
DBG_SWCLK, DBG_SWDIO,
NA
NA
NA
NA
CMU_OUT0, CMU_OUT1
NA
NA
USB_VREGI, USB_VREGO, USB_DM,
USB_DMPU, USB_DP
I2C0_SDA, I2C0_SCL
US0_TX, US0_RX. US0_CLK, US0_CS
US1_TX, US1_RX, US1_CLK, US1_CS
2015-05-06 - EFM32HG309FXX - _Rev0.91
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